Post Go back to editing

AD9102 Trigger and UPDATE bit (0x1D)

Hello everybody,

tried to send the registers which are in the example6.regval to FPGA, after that, I sent 0x01 to register 0x1D and then set Trigger high and low. But I have no Sine wave from DAC.

1- Should I repeat UPDATE bit (0x1D) for the trigger as well?

2- Is any specific time for trigger needed?

3- Is any specific time for UPDATE bit (0x1D) needed?

4- For Sine wave from DDS, should I write some data into the RAM? 

5- How can I read the sent data (from FPGA) through AD9102 software?

Regards,

Akbar



DDS
[edited by: akbar at 2:54 PM (GMT 0) on 30 Apr 2019]
Parents
  • Hello Akbar,

    1-4: no

    5: click on the "Register_Contents" tap at the bottom of the GUI.

    Regards,

    Will

  • Dear Will,

    after loading example6.regval, trigger high and low is done by "write active tab". 

    1- What does do the "write active tab" ? Which register and bit are going to be changed?

    2- Is the example6.regval a specific configuration for using the eval-Board and GUI ? 

    Was it a proper decision using the example6.regval configuration to communicate between FPGA and DAC ? (I did the same, but no output Sine wave)

    Regards,

    Akbar

  • Dear Akbar,

    1, You want to do it after you write the RAMUPDATE bit and bring CS_B high.

    2. Yes.

    Regards,

    Will

  • Dear Will,

    I did following:

    CS_B low, first address, data, CS_B high, again CS_B low and so on... for every address, finally Readback was sucssefull but still I have not any out put signal.

    Regards,

    Akbar

  • Dear Akbar,

    I am sorry to hear that.

    The register values that you read back after you wrote through FPGA, are they the same as the values that you read back (by clicking on Register_Contents tab) before you modified the board? How did you apply the trigger_B signal?

    Regards,

    Will

  • Dear Will,

    as far as I remember, they were the same, but I am not 100% sure. I will let you know on Monday.

    1- Referring to your suggestion, jumper jp1 is open and I have connected the TP30 directly to the Trigger port.

    2- Actually, with the logic (FPGA), the trigger is high as default. I don't know whether default hight is correct? 

    So I set it high again (or keep it high again) not after one clock cycle, but only a few u sec, then low and again a delay, after that Readback is executed.

    Regards,

    Akbar

  • Another thing is that the SRAM data are left aligned meaning the 12 bits are 15:4, not 11:0 as in the data sheet page 27. You may want to read back a few SRAM registers to make sure they are what you wrote.

    Regards,

    Will

  • Dear Will,

    I will write only 33 registers and readback 128 registers.

    33 registers are:

    x"0000",   data = x"0000", 
    x"0001",   data = x"0E00",  
    x"0002",   data = x"0000",  
    x"0003",   data = x"0000",  
    x"0007",   data = x"4000",  
    x"0008",   data = x"0000",  
    x"000C",   data = x"1F00",  
    x"000D",   data = x"0000",  
    x"000E",   data = x"0000",  
    x"001D",   data = x"0000",  
    x"001E",   data = x"0000",  
    x"001F",   data = x"0000",  
    x"0020",   data = x"000E",  
    x"0025",   data = x"0000",  
    x"0027",   data = x"1232",  
    x"0028",   data = x"0111",  
    x"0029",   data = x"0200",  
    x"002B",   data = x"0101",  
    x"002C",   data = x"0003",  
    x"002D",  data = x"0000",  
    x"0031",   data = x"0000", 
    x"0035",   data = x"4000",  
    x"0037",   data = x"7E00",  
    x"003E",   data = x"0750",  
    x"003F",   data = x"7500",  
    x"0043",   data = x"0000",  
    x"0044",   data = x"0002",  
    x"0045",   data = x"0000",  
    x"0047",   data = x"0000",  
    x"005C",   data = x"0FA0",  
    x"005D",   data = x"0000",  
    x"005E",   data = x"0000",  
    x"005F",   data = x"7FFF" 

    Write:

    Readback:

    I readback Reg0x01  as 00E7

    and

    I readback Reg0x02 as 0070. 

    Refering to datasheet, [2:0] for both Reg0x1 and Reg0x02 RESERVED bits.

    Are the read data correct, even the RESERVED bits

    Regards,

    Akbar

  • Dear Will,

    in this regard, I should mention that I want to generate Sin wave, so I guess there is nothing to deal with SRAM or did I get it wrong?

    Regards,

    Akbar

  • Dear Akbar,

    The read data are not correct. Reg0x01 is ok as [2:0] are reserve bits, but non-reserve bits on other registers (reg0x02 reg0x07) not match either.

    Can you zoom in on the reg0x02 and also include SCLK.

    Regards,

    Will

  • That is correct. If you just want sine wave, you should use the DDS functionality and you don't need SRAM (unless you want to modulate the sine wave with SRAM data).

    Will

  • Yellow is SCLK

    0x02:

    0x07:

    and 0x7F:

    0x0E:

    0x0B:

    0x0C, 0x0B, 0x0A, 0x09:

    Trigger is high, after 2ms is low:

    Here the Yellow is Trigger.

Reply Children