AD9102 Trigger and UPDATE bit (0x1D)

Hello Akbar,

1-4: no

5: click on the "Register_Contents" tap at the bottom of the GUI.

Regards,

Will

Dear Will,

after loading example6.regval, trigger high and low is done by "write active tab". 

1- What does do the "write active tab" ? Which register and bit are going to be changed?

2- Is the example6.regval a specific configuration for using the eval-Board and GUI ? 

Was it a proper decision using the example6.regval configuration to communicate between FPGA and DAC ? (I did the same, but no output Sine wave)

Regards,

Akbar

Dear Akbar,

I think what you are doing is fine. Just make sure that you can read back the correct values. Except the RAMUPDATE bit of course, since it is self clearing.

Regards,

Will

Dear Will,

Thank you again for your reply.

To Readback:

1- can I read immediately after sending last data?

Should I consider spesific time and then send the read command?

2- should I follow same procedure? (CS_B low, first address, data, CS_B high, again CS_B low and so on...).

Regards,

Akbar

Dear Akbar,

1, You want to do it after you write the RAMUPDATE bit and bring CS_B high.

2. Yes.

Regards,

Will

Dear Will,

I did following:

CS_B low, first address, data, CS_B high, again CS_B low and so on... for every address, finally Readback was sucssefull but still I have not any out put signal.

Regards,

Akbar

Dear Akbar,

I am sorry to hear that.

The register values that you read back after you wrote through FPGA, are they the same as the values that you read back (by clicking on Register_Contents tab) before you modified the board? How did you apply the trigger_B signal?

Regards,

Will

Dear Will,

as far as I remember, they were the same, but I am not 100% sure. I will let you know on Monday.

1- Referring to your suggestion, jumper jp1 is open and I have connected the TP30 directly to the Trigger port.

2- Actually, with the logic (FPGA), the trigger is high as default. I don't know whether default hight is correct? 

So I set it high again (or keep it high again) not after one clock cycle, but only a few u sec, then low and again a delay, after that Readback is executed.

Regards,

Akbar

Another thing is that the SRAM data are left aligned meaning the 12 bits are 15:4, not 11:0 as in the data sheet page 27. You may want to read back a few SRAM registers to make sure they are what you wrote.

Regards,

Will

Dear Will,

I will write only 33 registers and readback 128 registers.

33 registers are:

x"0000",   data = x"0000", 
x"0001",   data = x"0E00",  
x"0002",   data = x"0000",  
x"0003",   data = x"0000",  
x"0007",   data = x"4000",  
x"0008",   data = x"0000",  
x"000C",   data = x"1F00",  
x"000D",   data = x"0000",  
x"000E",   data = x"0000",  
x"001D",   data = x"0000",  
x"001E",   data = x"0000",  
x"001F",   data = x"0000",  
x"0020",   data = x"000E",  
x"0025",   data = x"0000",  
x"0027",   data = x"1232",  
x"0028",   data = x"0111",  
x"0029",   data = x"0200",  
x"002B",   data = x"0101",  
x"002C",   data = x"0003",  
x"002D",  data = x"0000",  
x"0031",   data = x"0000", 
x"0035",   data = x"4000",  
x"0037",   data = x"7E00",  
x"003E",   data = x"0750",  
x"003F",   data = x"7500",  
x"0043",   data = x"0000",  
x"0044",   data = x"0002",  
x"0045",   data = x"0000",  
x"0047",   data = x"0000",  
x"005C",   data = x"0FA0",  
x"005D",   data = x"0000",  
x"005E",   data = x"0000",  
x"005F",   data = x"7FFF" 

Write:

Readback:

I readback Reg0x01  as 00E7

and

I readback Reg0x02 as 0070. 

Refering to datasheet, [2:0] for both Reg0x1 and Reg0x02 RESERVED bits.

Are the read data correct, even the RESERVED bits? 

Regards,

Akbar

Dear Will,

in this regard, I should mention that I want to generate Sin wave, so I guess there is nothing to deal with SRAM or did I get it wrong?

Regards,

Akbar

Dear Akbar,

The read data are not correct. Reg0x01 is ok as [2:0] are reserve bits, but non-reserve bits on other registers (reg0x02 reg0x07) not match either.

Can you zoom in on the reg0x02 and also include SCLK.

Regards,

Will

Dear Akbar,

The read data are not correct. Reg0x01 is ok as [2:0] are reserve bits, but non-reserve bits on other registers (reg0x02 reg0x07) not match either.

Can you zoom in on the reg0x02 and also include SCLK.

Regards,

Will

Yellow is SCLK

0x02:

0x07:

and 0x7F:

0x0E:

0x0B:

0x0C, 0x0B, 0x0A, 0x09:

Trigger is high, after 2ms is low:

Here the Yellow is Trigger.

Dear Will,

as I mentioned previously,

1- I copied the registers from "example6.regal" and sent to AD9102,

2- due to unsuccessful result (sine wave), I only tried to send only 33 registers of the whole "example6.regal".

Consequently, it would be greatly appreciated

3- if you check these 33 registers and let me know whether they are correct or not:

33 registers are:

x"0000",   data = x"0000", 
x"0001",   data = x"0E00",  
x"0002",   data = x"0000",  
x"0003",   data = x"0000",  
x"0007",   data = x"4000",  
x"0008",   data = x"0000",  
x"000C",   data = x"1F00",  
x"000D",   data = x"0000",  
x"000E",   data = x"0000",  
x"001D",   data = x"0000",  
x"001E",   data = x"0000",  
x"001F",   data = x"0000",  
x"0020",   data = x"000E",  
x"0025",   data = x"0000",  
x"0027",   data = x"1232",  
x"0028",   data = x"0111",  
x"0029",   data = x"0200",  
x"002B",   data = x"0101",  
x"002C",   data = x"0003",  
x"002D",  data = x"0000",  
x"0031",   data = x"0000", 
x"0035",   data = x"4000",  
x"0037",   data = x"7E00",  
x"003E",   data = x"0750",  
x"003F",   data = x"7500",  
x"0043",   data = x"0000",  
x"0044",   data = x"0002",  
x"0045",   data = x"0000",  
x"0047",   data = x"0000",  
x"005C",   data = x"0FA0",  
x"005D",   data = x"0000",  
x"005E",   data = x"0000",  
x"005F",   data = x"7FFF" 

x"001D",   data = x"0001", 

By the way,

4- reminder:

the goal is to generate sine, triangle and square wave with AD9102. So, I have generated them using AD9102 Evaluation Board. 

Now, I must do the same, generating sine, triangle and square wave  but sending registers from FPGA to AD9102.

Regards,

Akbar

Dear Akbar,

The registers are double buffered, and they don't get updated until you write 0x1 to the RAMUPDATE register. Thus you can't read them back immediately.

Regards,

Will

Dear Will,

Thank you for the reply, yes, for sure I write 0x1 to the RAMUPDATE register. So I did.

Refering to your previouse responses in this topic, I write 0x1 to the RAMUPDATE register immediately after writing last register, then I read 128 registers back.

Regards,

Akbar

That is good. Although that is not the case that you showed in the plots yesterday. In those plots you read back immediately after write. Is the read back still wrong after you write RAMUPDATE?

Regards,

Will

Dear Will,

the readback looks strange, maybe wrong.

reading back these registers are following:

I do not write to 0x0A, 0x0B and 0x0C, but readback is "1F0A", refering to "example6.regal" they should be "1F0A", thus it's ok.

For 0x09, I write "1F0A", readback is "1F00", thus is not ok.

For 0x07, I write "4000", but readback is "0000". So is not ok.

Regards,

Akbar

Dear Akbar,

Many of the registers are for AD9106 and not applicable for AD9102. They include Reg0x09, 0x0A and 0x0B. Reg0x09 and 0x0C are legitimate, and you read back the default, so it appears that you didn't write the registers successfully.

The data sheet said reg0x09 defaults to 0x000A. I check the eval board I have and that is incorrect, the default read back 0x1F0A. Sorry for the datasheet error.

Regards,

Will

Dear Will,

furtheremore, refering to your suggestion, I set CS high after each address (Write command + address + data).

Should I set a delay like this?

The 32-bit data is transmitted by "CS low => delay => 16-bit address (SPI_CLK on) => delay => 16-bit parameter (SPI_CLK on)  => delay => CS high".

https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/22647/ad9102-fpga-communication/326571#326571

Regards,

Akbar

Sure. Replicating what the micro-controller does would be a great starting point.

Regards,

Will

Dear Will,

Why this information is not included in datasheet ?!

Regards,

Akbar