AD9102 Trigger and UPDATE bit (0x1D)

Hello Akbar,

1-4: no

5: click on the "Register_Contents" tap at the bottom of the GUI.

Regards,

Will

Dear Will,

after loading example6.regval, trigger high and low is done by "write active tab". 

1- What does do the "write active tab" ? Which register and bit are going to be changed?

2- Is the example6.regval a specific configuration for using the eval-Board and GUI ? 

Was it a proper decision using the example6.regval configuration to communicate between FPGA and DAC ? (I did the same, but no output Sine wave)

Regards,

Akbar

Dear Will,

Yes, I was able to get an output before I modified the board and I have undone the modification 4 or 5 times and the part still works correctly.

No, the board is not damaged.

Regards,

Akbar

Dear Akbar,

How did you modify the board? Were you able to read back the register values that the FPGA wrote into AD9102?

Regards,

Will

Dear Will,

I have removed the resistors between, XJP1, XJP3, XJP4, XJP5.

I have guessed that I need to readback the register values, I will do it.

Regards,

Akbar

Dear Will,

to WRITE,

I do the following:

1. send WRITE command and address  "0b1000 0000 0000 0000" through SDIO. I would like to start from address '0' to 007fh. (sending same values from example6.regval)

2. send data (to address '0') (0b0000 0000 0000 0000) through SDIO.

So I do like that only for the first address (which is '0') and for the next address, address 1, I do not send again the WRITE command and the corresponding address, but only I do send the next data, data 1, through SDIO, referring to the data sheet:

" The SPI port automatically increments the register address if CS stays low beyond the first data-word allowing writes to a set of contiguous addresses. "

I guess I did it not correct ?

3. Finally, I do writes a '1' to the UPDATE bit in the RAMUPDATE register (RAMUPDATE, Address 0x1D). Again,  send WRITE command and address through SDIO, then send data (to address '0x1D') through SDIO,

Regards,

Akbar

And you apply it through XP3? How do you apply trigger and reset?

Hello Will,

Yes. 

Regarding reset, I do nothing and trigger, as I mentioned previously, through TP30, I do it manually. Set to high (+) and low (-).  

I suggest disconnect RESET_B from micro-controller by removing R2. That way you also have the option of applying hardware reset without fight again uC.

• Dear Will,

so what about trigger ?

and the method which I write data from 0x00 to 0x007F, was it correct?

Regards,

Akbar

Dear Akbar,

For the trigger you want to make sure that jumper jp1 is open.

The way you write the SPI, you want to bring CS_B high after writing reg0x0, and low again before writing reg0x1, and leave it low for the remainder of the SPI writes.

If the SPI writes were not successful, you may also want to try writing each register separately (CS_B low, command, data, CS_B high).

Regards,

Will

Dear Will,

surprised hearing that!

You suggest "bring CS_B high after writing reg0x0, and low again before writing reg0x1, and leave it low for the remainder of the SPI writes."

So why it has not been mentioned in the datasheet? Or is it a suggestion in this case?

Regards,

Akbar

Dear Will,

surprised hearing that!

You suggest "bring CS_B high after writing reg0x0, and low again before writing reg0x1, and leave it low for the remainder of the SPI writes."

So why it has not been mentioned in the datasheet? Or is it a suggestion in this case?

Regards,

Akbar

Dear Akbar,

The datasheet did mention that but not in great detail. According to page 18 of the datasheet, "The SPI port automatically increments the register address if CS_B stays low beyond the first data-word allowing writes to or reads from a set of contiguous addresses." If you don't bring CS-B high after writing reg0x0, it may interpret the next write command as data for reg0x1.

Since reg0x0 is the configuration register, it is a good idea to finish the write by bring CS_B high, before proceeding to other registers.

Regards,

Will

Dear Will,

Thank you for your reply.

According to page 18 of the datasheet and as I understood, I brought CS_B low and kept it low, sent '0' [15] through SDIO as write command and '0' [14:0] as the address of Reg0x00. Then I sent the second byte '0' as data [15:0].

After that, for the second register and second data (Reg 0x01 to 0x7F), I did not send the next address, because SPI port automatically increments the register address if CS_B stays low.

Finally, for RAMUPDATE, Address 0x1D, I brought CS_B low, sent write command, address of Reg0x1D [14:0], then 0x01 as data for Reg0x1D.

Regards,

Akbar

Dear Akbar,

I think what you are doing is fine. Just make sure that you can read back the correct values. Except the RAMUPDATE bit of course, since it is self clearing.

Regards,

Will

Dear Will,

Thank you again for your reply.

To Readback:

1- can I read immediately after sending last data?

Should I consider spesific time and then send the read command?

2- should I follow same procedure? (CS_B low, first address, data, CS_B high, again CS_B low and so on...).

Regards,

Akbar

Dear Akbar,

1, You want to do it after you write the RAMUPDATE bit and bring CS_B high.

2. Yes.

Regards,

Will

Dear Will,

I did following:

CS_B low, first address, data, CS_B high, again CS_B low and so on... for every address, finally Readback was sucssefull but still I have not any out put signal.

Regards,

Akbar

Dear Akbar,

I am sorry to hear that.

The register values that you read back after you wrote through FPGA, are they the same as the values that you read back (by clicking on Register_Contents tab) before you modified the board? How did you apply the trigger_B signal?

Regards,

Will

Dear Will,

as far as I remember, they were the same, but I am not 100% sure. I will let you know on Monday.

1- Referring to your suggestion, jumper jp1 is open and I have connected the TP30 directly to the Trigger port.

2- Actually, with the logic (FPGA), the trigger is high as default. I don't know whether default hight is correct? 

So I set it high again (or keep it high again) not after one clock cycle, but only a few u sec, then low and again a delay, after that Readback is executed.

Regards,

Akbar

Another thing is that the SRAM data are left aligned meaning the 12 bits are 15:4, not 11:0 as in the data sheet page 27. You may want to read back a few SRAM registers to make sure they are what you wrote.

Regards,

Will

Dear Will,

I will write only 33 registers and readback 128 registers.

33 registers are:

x"0000",   data = x"0000", 
x"0001",   data = x"0E00",  
x"0002",   data = x"0000",  
x"0003",   data = x"0000",  
x"0007",   data = x"4000",  
x"0008",   data = x"0000",  
x"000C",   data = x"1F00",  
x"000D",   data = x"0000",  
x"000E",   data = x"0000",  
x"001D",   data = x"0000",  
x"001E",   data = x"0000",  
x"001F",   data = x"0000",  
x"0020",   data = x"000E",  
x"0025",   data = x"0000",  
x"0027",   data = x"1232",  
x"0028",   data = x"0111",  
x"0029",   data = x"0200",  
x"002B",   data = x"0101",  
x"002C",   data = x"0003",  
x"002D",  data = x"0000",  
x"0031",   data = x"0000", 
x"0035",   data = x"4000",  
x"0037",   data = x"7E00",  
x"003E",   data = x"0750",  
x"003F",   data = x"7500",  
x"0043",   data = x"0000",  
x"0044",   data = x"0002",  
x"0045",   data = x"0000",  
x"0047",   data = x"0000",  
x"005C",   data = x"0FA0",  
x"005D",   data = x"0000",  
x"005E",   data = x"0000",  
x"005F",   data = x"7FFF" 

Write:

Readback:

I readback Reg0x01  as 00E7

and

I readback Reg0x02 as 0070. 

Refering to datasheet, [2:0] for both Reg0x1 and Reg0x02 RESERVED bits.

Are the read data correct, even the RESERVED bits? 

Regards,

Akbar