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AD9102 Trigger and UPDATE bit (0x1D)

Hello everybody,

tried to send the registers which are in the example6.regval to FPGA, after that, I sent 0x01 to register 0x1D and then set Trigger high and low. But I have no Sine wave from DAC.

1- Should I repeat UPDATE bit (0x1D) for the trigger as well?

2- Is any specific time for trigger needed?

3- Is any specific time for UPDATE bit (0x1D) needed?

4- For Sine wave from DDS, should I write some data into the RAM? 

5- How can I read the sent data (from FPGA) through AD9102 software?

Regards,

Akbar



DDS
[edited by: akbar at 2:54 PM (GMT 0) on 30 Apr 2019]
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  • Hello Akbar,

    1-4: no

    5: click on the "Register_Contents" tap at the bottom of the GUI.

    Regards,

    Will

  • Dear Will,

    after loading example6.regval, trigger high and low is done by "write active tab". 

    1- What does do the "write active tab" ? Which register and bit are going to be changed?

    2- Is the example6.regval a specific configuration for using the eval-Board and GUI ? 

    Was it a proper decision using the example6.regval configuration to communicate between FPGA and DAC ? (I did the same, but no output Sine wave)

    Regards,

    Akbar

  • Dear Akbar,

    The "write active tab" associated with trigger high/low instruct the micro-controller to send out a trigger high (or low) signal to AD9102.

    1. "write active tab" write the SPI registers associated with the "active tab" ("BOARD CONFIG", "CONFIG", etc...) to the respective device. "BOARD CONFIG" to micro-controller, others to AD9102.

    2. Yes.

    Did you send out the trigger signal from the FPGA to AD9102?

    Regards,

    Will

  • Dear Will,

    2- therefore, it is expectable that I don't get any output signal.

    Yes, I send out the trigger signal from the FPGA to AD9102, both manually with a wire to "+" and then "-".

    3- Could you mind letting me know, which registers are configured specifically, for the eval-Board?

    Regards,

    Akbar

  • Dear Akbar,

    I am afraid I misunderstood your second question. "example6.regal" is a specific congifuration that can be used with the eval-board and GUI, but not JUST for the eval board and GUI. All the registers in the file are for AD9102, and should work either AD9102 is on the eval board or your own board.

    Does the trigger signal go directly to pin 32 or AD9102?

    The GUI communicate with the eval board through USB and the micro-controller PIC18F4550-I/ML. The micro-controller then communicate with AD9102 through SPI, as well as generate control signals. The "BOARD CONFIG" tab is for generating control signals, and all the other tabs are for SPI registers. (Tabs "DAC2", "DAC3" and "DAC4" are for AD9106 and not applicable for AD9102.) All the SPI registers are for AD9102.

    I hope it helps.

    Regards,

    Will

  • Dear Will,

    as I mentioned, I tried to send the configuration of the registers which are in "example6.regal" from FPGA to AD9102, but I couldn't get any output Sine wave. So I thought maybe the "example6.regal" is only for using the eval-board and GUI, now you say it should work either AD9102 on the eval-board or my own board.

    At the moment I don't use AD9102 on my own board, but only disconnected the SPI pins between the micro-controller PIC18F4550-I/ML and AD9102 and using FPGA instead of micro-controller PIC18F4550-I/ML.

    My attempt is to find out the problem, why I don't have an output wave.

    I have removed one of the resistors, which is related to the TP30 (for the trigger pin) so the trigger signal goes directly from FPGA to TP30.

    Regards,

    Akbar

  • Dear Akbar,

    Were you able to get an output before you modified the board? If not, then probably the board was defective or damaged; if yes, perhaps you can undo the modification and see if the part still works?

    Regards,

    Will

  • Dear Will,

    Yes, I was able to get an output before I modified the board and I have undone the modification 4 or 5 times and the part still works correctly.

    No, the board is not damaged.

    Regards,

    Akbar

  • Dear Akbar,

    How did you modify the board? Were you able to read back the register values that the FPGA wrote into AD9102?

    Regards,

    Will

  • Dear Will,

    I have removed the resistors between, XJP1, XJP3, XJP4, XJP5.

    I have guessed that I need to readback the register values, I will do it.

    Regards,

    Akbar

  • Dear Will,

    to WRITE,

    I do the following:

    1. send WRITE command and address  "0b1000 0000 0000 0000through SDIO. I would like to start from address '0' to 007fh. (sending same values from example6.regval)

    2. send data (to address '0') (0b0000 0000 0000 0000) through SDIO.

    So I do like that only for the first address (which is '0') and for the next address, address 1, I do not send again the WRITE command and the corresponding address, but only I do send the next data, data 1, through SDIO, referring to the data sheet:

    " The SPI port automatically increments the register address if CS stays low beyond the first data-word allowing writes to a set of contiguous addresses. "

    I guess I did it not correct ?

    3. Finally, I do writes a '1' to the UPDATE bit in the RAMUPDATE register (RAMUPDATE, Address 0x1D). Again,  send WRITE command and address through SDIO, then send data (to address '0x1D') through SDIO,

    Regards,

    Akbar

  • And you apply it through XP3? How do you apply trigger and reset?

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