DAC没有输出?

 

ADI的技术专家你们好,我在项目中要做矢量信号源,DAC采用了AD9152,时钟采用100M REFclk,

SYSREF=1.5625Mhz, 采用锁相环倍频方式,jesd204B模式采用4模式,使用两个通道做IQ,

数据率datarate=400M,lanerate=4Gbps,fDAC=1.6GSPS,4倍插值。FPGA采用XILINXKINTEX7,使用了jesd204B IP核,已经完成了1Code Group Synchronization2Initial Lane Alignment Sequence3Step 3: Data Streaming,时序图如下图

通过寄存器回读地址寄存器0x400~426(FPGAJESD204B的参数)0x450~45D完全一致,从地址0x470~473中回读到的数据为0x0f,说明发射端FPGA到接收端DAC已经完成了代码组同步,初始序列对齐,以及校验和的匹配。

其他的回读数据如下:

1)地址0x023   数据0x08    serplllock

地址0x024   数据0x08    overflow

地址0x025   数据0x00    serplllock

地址0x03D   数据0x0D    SYNCLOCK SYNCROTATE

地址0x084   数据0x2a    DAC_PLL_LOCK

地址0x08E   数据0x07    CLK_ON   IS_DIFF  CLK_DET_EN

地址0x281   数据0x0B    SERDES_PLL_CAL_VALID SERDES_VCO_CAL_PEOGRESS SERDES_PLL_LOCK

但是就是没有数据输出,询问了北京的ADI技术支持建议使用内部DDS试一试,我设置了DDS,更新地址0x113  进行了FTW_UPDATE_ REQ,但是bit[1]=0, FTW_UPDATE_ ACK=0,why?

同样还有一个问题,我使能了温度传感器,读到的数为0,如何使用内部温度传感器?

以下是我的寄存器详细流程以及电路原理图,请专家能不能发现问题,谢谢

  case(addr_index)

 8'h00           : begin  reg_data <= 24'h0000BD; end  // Soft reset

 8'h01           : begin  reg_data <= 24'h000000; end  // Soft reset

 8'h02           : begin  reg_data <= 24'h001100; end  //  Enable the reference, DAC channels, and clocks

 8'h03           : begin  reg_data <= 24'h008004; end  // Enable duty cycle correction

 8'h04           : begin  reg_data <= 24'h008104; end  // Power up the SYSREF± receiver, disable hysteresis   

8'h05           : begin  reg_data <= 24'h01CDD8; end  // Band gap configuration

8'h06           : begin  reg_data <= 24'h008E01; end  //CLK_DECTEC

8'h07           : begin  reg_data <= 24'h012f21; end  //TEMP_SENSOR_ENABLE

8'h08           : begin  reg_data <= 24'h013401; end  //DIE_TEMP_UPDATE

          ///* Required Device Configurations */

8'h09           : begin  reg_data <= 24'h028462; end //SERDES PLL configuration

8'h0A           : begin  reg_data <= 24'h0285C9; end //SERDES PLL configuration

8'h0B           : begin  reg_data <= 24'h02860E; end //SERDES PLL configuration

8'h0C           : begin  reg_data <= 24'h028712; end //SERDES PLL configuration       

8'h0D           : begin  reg_data <= 24'h028A2B; end //  See Table 36 

8'h0E           : begin  reg_data <= 24'h028B00; end  //SERDES PLL configuration

8'h0F           : begin  reg_data <= 24'h029089; end  //SERDES PLL configuration

8'h10           : begin  reg_data <= 24'h02914C; end //  See Table 36 

8'h11           : begin  reg_data <= 24'h029424; end   //SERDES PLL configuration

8'h12           : begin  reg_data <= 24'h029603; end //  See Table 36 

8'h13           : begin  reg_data <= 24'h02970D; end     //SERDES PLL configuration

8'h14           : begin  reg_data <= 24'h029902; end     //SERDES PLL configuration

8'h15           : begin  reg_data <= 24'h029A8E; end     //SERDES PLL configuration  

8'h16           : begin  reg_data <= 24'h029C2A; end    //SERDES PLL configuration

8'h17           : begin  reg_data <= 24'h029F7E; end    //SERDES PLL configuration

8'h18           : begin  reg_data <= 24'h02A006; end    //SERDES PLL configuration

          /* Required DAC PLL Configuration */

8'h19           : begin  reg_data <= 24'h008D7B; end      //DAC PLL configuration

8'h1A           : begin  reg_data <= 24'h01B000; end      //DAC PLL configuration

8'h1B           : begin  reg_data <= 24'h01B924; end      //DAC PLL configuration

8'h1C           : begin  reg_data <= 24'h01BC0D; end      //DAC PLL configuration   

8'h1D           : begin  reg_data <= 24'h01BE02; end      //DAC PLL configuration

8'h1E           : begin  reg_data <= 24'h01BF8E; end      //DAC PLL configuration

8'h1F           : begin  reg_data <= 24'h01C02A; end      //DAC PLL configuration   

8'h20           : begin  reg_data <= 24'h01C47E; end      //DAC PLL configuration

8'h21           : begin  reg_data <= 24'h01C12C; end      //DAC PLL configuration

          /* Configure the DAC PLL */

8'h22           : begin  reg_data <= 24'h008B01; end    //Set the VCO LO divider to 8 such that 6 GHz fVCO = fDAC × 2(LODivMode + 1) 12 GHz.  fDAC=1600MHz

8'h23           : begin  reg_data <= 24'h008C01; end   //Set the reference clock divider to 8 so that the reference clock into the PLL is less than 80 MHz. clkref=100MHz

8'h24           : begin  reg_data <= 24'h008510; end    // Set the B counter to 16 to divide the DAC clock down to 2× the reference clock.

8'h25           : begin  reg_data <= 24'h01B649; end   //See Table 73

8'h26           : begin  reg_data <= 24'h01B5C9; end   //See Table 73

8'h27           : begin  reg_data <= 24'h01BB12; end   //See Table 73

8'h28           : begin  reg_data <= 24'h01B478; end   //Optimal DAC PLL VCO settings.

8'h29           : begin  reg_data <= 24'h01C506; end   //See Table 73

8'h2A           : begin  reg_data <= 24'h008A12; end   //Optimal DAC PLL VCO settings.

8'h2B           : begin  reg_data <= 24'h008762; end   //Optimal DAC PLL loop filter

8'h2C           : begin  reg_data <= 24'h0088C9; end   //Optimal DAC PLL loop filter

8'h2D           : begin  reg_data <= 24'h00890E; end   //Optimal DAC PLL loop filter

8'h2E           : begin  reg_data <= 24'h008310; end   //disable the DAC PLL

          //DIGITAL DATAPATH

8'h2F           : begin  reg_data <= 24'h011202; end    //Set the interpolation to 4×.

8'h30           : begin  reg_data <= 24'h011000; end    // Set twos complement data          8'h31           : begin  reg_data <= 24'h0111B2; end    //  DATAPATH_CTRL NCO Fine  Modulation  INVERSE SINC                                        

     //   Programmable Modulus DDS

8'h32           : begin  reg_data <= 24'h011400; end    //FTW0

8'h33           : begin  reg_data <= 24'h011500; end    //FTW1

8'h34           : begin  reg_data <= 24'h011600; end    //FTW2

8'h35           : begin  reg_data <= 24'h011700; end    //FTW3

8'h36           : begin  reg_data <= 24'h011800; end    //FTW4

8'h37           : begin  reg_data <= 24'h011910; end    //FTW5

8'h38           : begin  reg_data <= 24'h015200; end    //ACC_MODULUS0

8'h39           : begin  reg_data <= 24'h015800; end    //ACC_DELTA0

8'h3A           : begin  reg_data <= 24'h011A00; end    //ACC_MODULUS0

8'h3B           : begin  reg_data <= 24'h011B00; end    //ACC_DELTA0     

8'h3C           : begin  reg_data <= 24'h011301; end    //NCO_FTW_UPDATE

8'h3D           : begin  reg_data <= 24'h012C00; end    //DACOFF  PROTECT_ MODE

          //If this bit is high then DAC is in protect mode, and DAC is shut down automatically when some errors happen.

          //If this bit is high and Bit 7 is high, then if input average power is bigger than given threshold

          // within a given time window, DAC output shuts down automatically.

8'h3E           : begin  reg_data <= 24'h013501; end    //DC_OFFSET_CTRL Enables dc offset module.

8'h3F           : begin  reg_data <= 24'h015131; end    //DATAPATH_CTRL2 Programmable FIR demodulation enable Programmable FIR enable Modulus enable

8'h40           : begin  reg_data <= 24'h020000; end  //Power up the interface

8'h41           : begin  reg_data <= 24'h020100; end  //Enable all lanes  

8'h42           : begin  reg_data <= 24'h030000; end  //First power down JESD204B digital (by default)

8'h43           : begin  reg_data <= 24'h045000; end  //Set the device DID to match Tx (0x00 in this example)

8'h44           : begin  reg_data <= 24'h045100; end  //Set the bank BID to match Tx (0x00 in this example)

8'h45           : begin  reg_data <= 24'h045200; end  //Set the lane LID to match Tx (0x00 in this example)

8'h46           : begin  reg_data <= 24'h045383; end    //Set descrambling and L = 4 (in n ? 1 notation)

8'h47           : begin  reg_data <= 24'h045400; end    //Set F = 1 (in n - 1 notation)

8'h48           : begin  reg_data <= 24'h04551F; end    //Set K = 32 (in n - 1 notation)

8'h49           : begin  reg_data <= 24'h045601; end    //Set M = 2 (in n - 1 notation)

8'h4A           : begin  reg_data <= 24'h04570F; end    //Set N = 16 (in n - 1 notation)

8'h4B           : begin  reg_data <= 24'h04582F; end    //Set Subclass 1 and NP = 16 (in n - 1 notation)

8'h4C           : begin  reg_data <= 24'h045920; end    //Set JESD204B Version and S = 1 (in n - 1 notation)

8'h4D           : begin  reg_data <= 24'h045A00; end    //Set D=HD

8'h4E           : begin  reg_data <= 24'h045B00; end    //Set RES1

8'h4F           : begin  reg_data <= 24'h045C00; end    //Set RES2

8'h50           : begin  reg_data <= 24'h045D45; end    //Set checksum for Lane 0 Checksum for Lane 0. Calculated checksum.

8'h51           : begin  reg_data <= 24'h046C0F; end     //Deskew Lane 0 to Lane 3

8'h52           : begin  reg_data <= 24'h047601; end    //Set F (not in n - 1 notation)

8'h53           : begin  reg_data <= 24'h047D0F; end    //Enable Lane 0 to Lane 3

      //    PHYSICAL LAYER

8'h54           : begin  reg_data <= 24'h02A701; end    //Autotune PHY setting

8'h55           : begin  reg_data <= 24'h031401; end    //SERDES SPI configuration

8'h56           : begin  reg_data <= 24'h023009; end    //Configure CDRs in half rate mode and set the SYNCOUT± swing VOD to 350 mV

8'h57           : begin  reg_data <= 24'h020600; end    //Resets CDR logic

8'h58           : begin  reg_data <= 24'h020601; end    //Release CDR logic reset

8'h59           : begin  reg_data <= 24'h028901; end    //Set the CDR oversampling for PLL

8'h5A           : begin  reg_data <= 24'h028001; end    //SPLLDivEnable the SERDES PLL.2

8'h5B           : begin  reg_data <= 24'h026862; end    //EqMode

     //   DATA LINK LAYER 

8'h5C           : begin  reg_data <= 24'h030101; end    //Set the subclass = 1

8'h5D           : begin  reg_data <= 24'h030400; end    //Set the LMFC delay setting to 0

8'h5E           : begin  reg_data <= 24'h03060A; end    //Set the LMFC receive buffer delay to 10

8'h5F           : begin  reg_data <= 24'h003A02; end    //Set sync mode = one shot sync

8'h60           : begin  reg_data <= 24'h003A82; end    //Enable the sync machine

8'h61           : begin  reg_data <= 24'h003AC2; end//

8'h62           : begin  reg_data <= 24'h030001; end//Bit 0 = 1 to enable Link 0.

原理图

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