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Q&A What is "N2[1:0] PLL control clock divider" in AD9146?

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What is "N2[1:0] PLL control clock divider" in AD9146?

Sergo_R on Mar 21, 2019

What is it for?

Thanks

0 deljones

on Oct 28, 2019 6:49 PM
This is to divide down the input clock in case you are supplying a reference at a multiple of the sampling frequency you wish to use.
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