When using JESD, are the DACs (e.g. AD9163 and AD9164) going to have issue if we start to shift the phase of the clock? If so, is LVDS a way around this (e.g. LTC2000)? We are thinking of shifting the clock by about 50ps for equivalent time sampling.
Thanks in advance.
Hello, what DAC sample rate will you be using?
in general, while the DAC is in operation, any shift in the phase or frequency of the DAC clock has to be done so slowly otherwise the DAC's DLL will loose the lock condition and you need to reset the DAC to reconfigure the DLL and JESD PLL. As my colleague has pointed out, a 50ps phase shift in the clock depends on the DAC clock frequency; it can be either a very small change or a large one compared to the DAC clock frequency.