We are using the AD9102 to perform DDS output modulation from the SRAM. We need to have a waveform output that starts with a specific pattern (approx. 10% of the SRAM) and then changes to a different pattern (the other 90% of the SRAM) and this second pattern repeats forever. Our idea is to store both patterns in SRAM and start the output running. After the SRAM has played out the first pattern AND while its running, change the SRAM start address to the beginning of the second pattern so that when the SRAM gets to the Stop address and repeats, it repeats only the second pattern endlessly. For example, say samples 0:100 are the first pattern and samples 101 to 4095 are the second, we would initially set the Start address to 0 and end address to 4095. Then start the output, it would start at 0 and output past 100 and while it is outputting samples 101 to 4095 we would time our update to the SPI to reset the start address to 101 so that when it finishes sample 4095 and repeats, it would go back and play out samples 101:4095 on successive cycles. Therefore the final output would be 0:4095, 101:4095, 101:4095.... etc.
Is this possible ? If not, do you have any suggestions to achieve this type of capability ?
Next, several posts have indicated an update to the AD9102 datasheet (to at least Rev A) but Rev 0 is the only version I see on the web site. Revision 0 shows (page 27) that the SRAM_DATA is stored in address 0x6000 to 0x6FFF in bits 11:0 (ie only 12 bits) but other posts indicate the values are stored in bits 15:4 (again only 12 bits) while others indicate that values are truly 14bits as advertised and stored in 15:2. Please provide a link to the most up to date datasheet and please confirm the bit sizes and placements.