I have designed a multi-channel AWG board with several AD9162 chips. One design objective is channel-to-channel output skew less than 10 picosecond, so it is necessary to adjust the phase of DAC sample clocks.
All AD9162 are working at direct RF synthesis mode, all interpolation filters bypassed. A coarse alignment can be achieved easily, by ajdusting the deterministic delay of JESD204B Subclass1 and the sample phase offset readed from register 0x037 and 0x038. However, after this coarse alignment the channel-to-channel output skew is limited to the phase difference of DAC sample clocks.
In the section "Analog Interface Considerations" of AD9162 datasheet (Rev C.), it notes that a DLL is used to lock the DAC sample clock and the input clock, on Page 79. However, the details of how DLL works and affects DAC sample clock is not clear. The datasheet only suggests me to use default register values. In the section "Register Details", register 0x094, 0x095 and 0x096 look like the parameters to adjust the time delay or phase offset between input clock and sample clock. Could you give me some details about them?
We still strongly recommend to use "default register values" for the DLL unless you have a good solid understanding of how DLLs work. If so, you'll find it out that a DLL delays input clock rather than…