How to adjust DAC sample clock phase among multi AD9162s

Dear Sir/Madam,

I have designed a multi-channel AWG board with several AD9162 chips. One design objective is channel-to-channel output skew less than 10 picosecond, so it is necessary to adjust the phase of DAC sample clocks.

All AD9162 are working at direct RF synthesis mode, all interpolation filters bypassed. A coarse alignment can be achieved easily, by ajdusting the deterministic delay of JESD204B Subclass1 and the sample phase offset readed from register 0x037 and 0x038. However, after this coarse alignment the channel-to-channel output skew is limited to the phase difference of DAC sample clocks. 

In the section "Analog Interface Considerations" of AD9162 datasheet (Rev C.), it notes that a DLL is used to lock the DAC sample clock and the input clock, on Page 79. However, the details of how DLL works and affects DAC sample clock is not clear. The datasheet only suggests me to use default register values. In the section "Register Details", register 0x094, 0x095 and 0x096 look like the parameters to adjust the time delay or phase offset between input clock and sample clock. Could you give me some details about them?

Best regards

correct spelling
[edited by: fassd324 at 6:40 AM (GMT 0) on 25 Dec 2018]
  • We still strongly recommend to use "default register values" for the DLL unless you have a good solid understanding of how DLLs work. If so, you'll find it out that a DLL delays input clock rather than creating a new clock with an oscillator. To delay the input clock it needs delay cells and coarse and fine delay cells are used to do so. Because of just delaying the input clock, any phase noise with the input clock is transferred to the DAC core directly and no clock cleaning or synthesizing is done via the DLL block.

    Also, there is a control state machine which looks for the ideal delay line value. In the phase search/slope detection mode the controller is looking for the ideal DLL Coarse and Fine values before going into tracking mode. The delay line settings are ideal when the phase is equal to the target value and slope of the phase detector is at the programmed polarity.

    The phase search starts with the DLL Coarse and Fine set to the values programmed in Reg. 0x094 and 0x095. The algorithm begins to sweep through the DLL Coarse values until the target phase is measured. It is also possible for the DLL Coarse to step over the desired measured value. In this case, crossing the target phase will trigger the algorithm to move to the slope measurement step. This target value is user selectable in Reg. 0x096. When the desired phase is measured, the slope of the phase measurement is calculated by sweeping the DLL Fine and compared against the desired slope. The desired slope can be changed using Reg. 0x091. If the slope and phase match, the phase search and slope detection steps are complete. If the phase detector is not on the desired slope, the DLL Coarse will continue searching.

    I hope this helps you understand the DLL implemented in this chip better.

  • i have the same requirement. did you succeed in delaying the clock with the DLL registers?