I set AD9163 and related devices once. AD9163 settings are based on table41-43.
when I set AD9163 registers with the same values again, I got the attached output.
what is the cause of the problem?
How can I fix this?
upperside picture is for the normal result.
lower picture is for the abnormal one.
what is the test platform? is it our eval board, AD9163-FMCC-EBZ plus ADS7-V2 FPGA board?
But, it's similar to AD9163-FMCC-EBZ, containing ADF4355 and AD9508.
I further investgated the cause of the problem and found the problem is caused by the phase relationship between DAC clock and SYSREF.
Would you teach me if I can find the phase relationship from register values?
and what do 0x037-0x038 register value mean and relationship between them and register(0xF80-0xFE0) values?
In the datasheet on page 54, we have talked extensively about registers 0x037/38 and how to interpret their values. Regarding registers(0xF80-0xFE0), we don't have such registers in this product. However, if you are referring to the values, they can be interpreted as below:
1111-1110-0000 è rising edge of SYSREF is sampled at 0x DAC clock cycle delay with reference to the rising edge of divide-by-4 clock
1111-1100-0000 è rising edge of SYSREF is sampled at 1x DAC clock cycle delay with reference to the rising edge of divide-by-4 clock
1111-1000-0000 è rising edge of SYSREF is sampled at 2x DAC clock cycle delay with reference to the rising edge of divide-by-4 clock
1111-0000-0000 è rising edge of SYSREF is sampled at 3x DAC clock cycle delay with reference to the rising edge of divide-by-4 clock
Based on your info, I drew the timing chart (DAC CLK, SYSREF) for each register value(0xFE0-F00) below.
Would you comfirm if my understanding is correct.
This is correct