Hello,I have a question from our customer about AD9162 which is using in NCO mode.The situation is followings.The customer configures the registers of AD9162 after H/W reset.He spent 160us to set the registers.AD9162 output the signal after 300us after reset.So, 140us is needed to output after setting the registers.He noticed that the output signal appear after setting of IRQ_DATA_READY".He is doubting that the output timing is affected by JESD I/F.He wants to make the output timing shorter than 300us.Does it able to shorter by setting of register ?The SERDES is power downed.(0x200 = 0x01)Best regards,y-suzuki
As you know, this delay depends on the DAC Clk frequency and pipeline delay due to the different configurations that you pick for the DAC. If you use " Pipeline Delay (Latency) for Various DAC Blocks" table, you'll find the delay number based on the DAC clock cycles for you application. 48 DACCLK is the minimum latency in NCO only mode. If a 6GHz clock is used, 8ns of pipeline delay can be achieved.
However, in addition to the pipeline delay, you need to know how many SPI operations you need to update the output. For example, if you already load the FTW registers, to just update the output frequency, you need a single SPI write action which turns out to be 260ns.
So you need to calculate the number of SPI write actions, SPI clock rate, DAC Clock rate, and number of DSP blocks you are using.
In addition to the above reply. In case I am using automatic update mode and writing single word to the MSB byte of FTW for auto update. The total time required to change the frequency is 8 SPI clock cycle+260ns. If I use SPI clock of 50MHz, total time for frequency update is 260+(8*20)=420ns. Please correct me.