AD9116 DCLKIO CLKIN shared data bus and simultaneous synced output

We typically use a DAC with WRT_A, B lines but we want to switch to 1.8V logic.

We cannot find any DAC like AD9765 with silmutaneous update feature for 1.8V.

Therefore we are thinking about to use 6 AD9116 with a shared databus and sperate clk lines for each DAC.

Beside any fanout issues ...

Is it possible to delay and synchronize the output of all DAC with the CLKIN rising HIGH edge ?

How the retimer circuit comes into account and what is the expected latency. We have a window

of about 100ns for programming all.


time |-------------------  100ns --------------------------------------------------------------------------------------|-------------------------------------- ....


DAC1: DCLKIO  __|------|______________________________________________________

DAC2: DCLKIO  ________|------|________________________________________________

DAC3: DCLKIO  ______________|------|__________________________________________

DAC4: DCLKIO  ____________________|------|____________________________________

DAC5: DCLKIO  __________________________|------|______________________________

DAC6: DCLKIO  ________________________________|------|________________________

time |-------------------  100ns --------------------------------------------------------------------------------------|-------------------------------------- ....

Update DAC

DAC1: CLKIN     __________________________________________________________________|------|_________

DAC2: CLKIN     __________________________________________________________________|------|_________

DAC3: CLKIN     __________________________________________________________________|------|_________

DAC4: CLKIN     __________________________________________________________________|------|_________

DAC5: CLKIN     __________________________________________________________________|------|_________

DAC6: CLKIN     __________________________________________________________________|------|_________


DAC1: DCLKIO  __________________________________________________________________|------|_________

DAC2: DCLKIO  ________________________________________________________________________|------|___




  • +1
    •  Analog Employees 
    on Nov 15, 2018 8:59 PM

    Hello Mark,

    Yes, I think it will work. You might need to tinker with Retimer register 0x14 though.

    On the bottom of your drawing, DAC1 DCLKIO is aligned with CLKIN. I think you want to delay that until after CLKIN to avoid the possibility of DAC1 come out 1 sample ahead of others.