I'm trying to determine if I need subclass 1 or not and was a bit confused.
Looking at this diagram from the AD9164 datasheet, it seems like the variable latency occurs before the data phase:
I don't mind different startup latencies but I was wondering if this affected the actual data phase. The FPGA will send 0s to the DAC until it is ready to transmit a waveform. From the time when the FPGA decides to send the waveform to it actually outputting, does this latency remain constant throughout power cycles? Is this affected by deterministic latency?
If you are not planing to synchronize multiple DACs together and don't need fixed latency from PoR (Power-on-Reset) you won't need Subclass1.
Even in the Subclass0, while the DAC is on, the latency of the device doesn't change unless you change configuration of the DAC (like choosing a different interpolation filter).
Thanks, that makes sense.
How about if I want to synchronize two DACs using the same situation as above (don't care about fixed latency from PoR but do care about data latency). If I manually delay the samples in the FPGA to sync the two DACs, does the delay setting have to change every power cycle?
If you use the DACs in subclass1 mode and synchronize them by reading back the SYSREF_PHASEx registers and manually delay samples in the FPGA, the delay setting should stay the same from PoR to PoR according to the JESD204B standard. However, in our device, there is a randomness in sampling SYSREF due to the internal divide-by-4 clock. That is, from PoR to PoR, rising edge of the SYSREF signal might be sampled within any 4 phases of the DAC clock related to /4 clock. So this requires us to go through another synchronization process from PoR to PoR.
saberbf What kind of "different synchronization process from PoR to PoR" are you talking about? Can I get knowledge about the phase state (1 out of 4) ? Or do I have to live with the fact that my data will be output "somewhere" between 1..4 DACCLK cycles? For a phased-array design, phase offsets between converters must be known and deterministic without any variance from PoR to PoR.
Thanks for any clarifications!
@mikaelis, please refer to the datasheet for the complete read on how to setup the DAC in deterministic latency mode. We have lots of clarifying information there.
from POR to POR you need to go through synchronization process because the SYSREF signal is not there anymore and the DAC internal clock circuit is reset.