Deterministic Latency in the data phase

I'm trying to determine if I need subclass 1 or not and was a bit confused.

Looking at this diagram from the AD9164 datasheet, it seems like the variable latency occurs before the data phase:

I don't mind different startup latencies but I was wondering if this affected the actual data phase. The FPGA will send 0s to the DAC until it is ready to transmit a waveform. From the time when the FPGA decides to send the waveform to it actually outputting, does this latency remain constant throughout power cycles? Is this affected by deterministic latency?

Thanks,

-mike