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AD9102 DAC Constant, Gain, Offset

Hi all,

I'm working with the AD9102 chip and manage to get some of the provided examples to work as expected.

Now I'm trying to simple put out a dc constant value to the DAC setting the waveform selector to the DC Constant selector. The parameters aimed to be used is the Constant generator value using the DAC_CONST parameter, as well as Gain and Offset using DAC_DIG_GAIN and DAC_DIG_OFFSET. 

This might seem to be a simple setup but I simple doesn't get it to work right. Either the DAC generates an output using only the DAC_CONST value (ignoring any gain and offset setting), or the opposite.

The setup used is according to below:

#Init (Address+Data)
SPI, 0x0000 0000
SPI, 0x0001 0000
SPI, 0x0002 0000
SPI, 0x000c 8f0a
SPI, 0x001f 0000

# WAV Config
SPI, 0x0027 0100 # See comments below

# DAC Constant, Gain, Shift
SPI, 0x0031 2000
SPI, 0x0035 2000
SPI, 0x0025 1000

# RAM Update and RUN
SPI, 0x001d 0001
SPI, 0x001e 0001

# Send Trigger, falling edge active low.

Using the setting above it seems that the DAC Constant value is used prior the trigger is sent. 7FFF corresponds to full range. With this board 1 V corresponds to 4mA. The value scales good setting 4000, 2000, 1000 etc. Also negative values like 8000 is working.

Any value on Gain and offset is ignored prior to the trigger is sent

After the trigger is sent, a value that seems to be roughly half maximum seems to be used as input to the gain and offset (from RAM? From somewhere else?). Gain = 0x400 (1) and Offset = 0x000 gives about 0.5 V output. Gain 7FFF gives 1V, 0x2000 0.25 etc. The offset value also scales as expected.

But, the value on DAC_CST is ignored after the trigger is sent.

I also tried the 4 different configurations on the lower 2 bits of the WAVCONFIG register. What changes is that after a trigger the output is not updated at all.

So, what is wrong with the setup or does the chip not support what I like to do? For example, does setup with Constant not support gain and offset and is directly input to the DAC when RAMUPDATE is written? Or do I setup the chip incorrectly for using Constant together with gain and offset?

Appreciate your support.

Thanks,
Martin



Typo correction on DAC digital offset address.
[edited by: MartinPe at 7:26 AM (GMT -5) on 9 Nov 2018]
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  • Hello Martin,

    Sorry that you are having trouble working with the part!

    Two questions regarding your SPI writes. "SPI, 0x0027 0100 # See comments below" is writing into reserved bit<8>, and "SPI, 0x0024 1000" is trying to access an address that doesn't exist in AD9102. Should it be 0x0025, DAC digital offset instead?

    Regards,

    Will

  • Hi William,

    Thanks for the quick reply.

    For the 0x0027 register, the reset value is 0x0101. So the reserved bit 8 is only kept at the same configuration. I did try to change the value to '0' but no change in behaviour.

    Right, it was a typo for the DAC digital offset address (only here), code was correct). I will see if possible to adjust the post above.

    Regards,
    Martin

  • Hello Martin,

    Sorry for the delay as I needed to set up a board to verify your observation.

    It is true to digital gain (reg0x35) and digital offset (reg0x25) do not apply in DAC constant value mode. By the way, you need to write reg0x27 0x0001 instead of 0x0100 as shown. So the front-page diagram is not accurate, as it does give the impression that digital gain and offset also apply to the constant mode.

    The constant mode does not need trigger. Trigger is for reading through RAM, and digital gain and offset does apply in RAM mode. Since you set reg0x27 to 0x0100 as shown, it is in "RAM" mode. Before you sent trigger, it operates in the default "constant" mode, in which digital gain and offset do NOT apply; and the trigger signal switches it over to RAM mode, in which digital gain and offset DO apply.

    Regards,

    Will

Reply
  • Hello Martin,

    Sorry for the delay as I needed to set up a board to verify your observation.

    It is true to digital gain (reg0x35) and digital offset (reg0x25) do not apply in DAC constant value mode. By the way, you need to write reg0x27 0x0001 instead of 0x0100 as shown. So the front-page diagram is not accurate, as it does give the impression that digital gain and offset also apply to the constant mode.

    The constant mode does not need trigger. Trigger is for reading through RAM, and digital gain and offset does apply in RAM mode. Since you set reg0x27 to 0x0100 as shown, it is in "RAM" mode. Before you sent trigger, it operates in the default "constant" mode, in which digital gain and offset do NOT apply; and the trigger signal switches it over to RAM mode, in which digital gain and offset DO apply.

    Regards,

    Will

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  • Hi William,

    Thanks for the clarification on this item.

    This implies that the Constant mode will be limited to 12 bit if you include both positive and negative range.

    If you like to make use of all 14 bit given a static output, would you recommend using a 14-bit value in the SRAM? Optionally with or without the DAC Offset parameter.

    The next use case is to slowly (meaning more or less static) looping through all 14-bit values. I see three options. 1) Updating the value in the SRAM 2) Program the SRAM and step the address. Need to be looped a few times. 3) Use fixed value on SRAM and Step the DAC Offset (12 bit). Use 4 values on the SRAM.

    Is it some solution you think is preferably compared to the others?

    Thanks again for the support.

    Regards,
    Maritn

  • Hello Martin,

    This implies that the Constant mode will be limited to 12 bit if you include both positive and negative range.

    Correct.

    If you like to make use of all 14 bit given a static output, would you recommend using a 14-bit value in the SRAM? Optionally with or without the DAC Offset parameter.

    Yest. Although SRAM is also 12bit, so you do need to use digital offset to truly get 14bit.

    The next use case is to slowly (meaning more or less static) looping through all 14-bit values. I see three options. 1) Updating the value in the SRAM 2) Program the SRAM and step the address. Need to be looped a few times. 3) Use fixed value on SRAM and Step the DAC Offset (12 bit). Use 4 values on the SRAM.

    I think #3 will work. The first two won't give you true 14bit as the SRAM is only 12bit.

    Regards,

    Will

  • Hi William,

    Thanks again.

    For the size of the SRAM, could you confirm this? The specification states both 12 and 14 bits (several times).

    Best regards,
    Martin

  • The SRAM is 14bit wide as verified by low level SPI controller. Sorry for the inconsistency in data-sheet.

  • Thanks again for confirming William.

    Best regards,
    Martin

  • Oh, and the datasheet said the active bits are <11:0>(12 LSBs), they are actually <15:2>(14MSBs). Again, my apologies for the datasheet error.