AD9102 DAC Constant, Gain, Offset

Hello Martin,

Sorry that you are having trouble working with the part!

Two questions regarding your SPI writes. "SPI, 0x0027 0100 # See comments below" is writing into reserved bit<8>, and "SPI, 0x0024 1000" is trying to access an address that doesn't exist in AD9102. Should it be 0x0025, DAC digital offset instead?

Regards,

Will

Hi William,

Thanks for the quick reply.

For the 0x0027 register, the reset value is 0x0101. So the reserved bit 8 is only kept at the same configuration. I did try to change the value to '0' but no change in behaviour.

Right, it was a typo for the DAC digital offset address (only here), code was correct). I will see if possible to adjust the post above.

Regards,
Martin

Hi William,

Thanks for the quick reply.

For the 0x0027 register, the reset value is 0x0101. So the reserved bit 8 is only kept at the same configuration. I did try to change the value to '0' but no change in behaviour.

Right, it was a typo for the DAC digital offset address (only here), code was correct). I will see if possible to adjust the post above.

Regards,
Martin

Hello Martin,

Sorry for the delay as I needed to set up a board to verify your observation.

It is true to digital gain (reg0x35) and digital offset (reg0x25) do not apply in DAC constant value mode. By the way, you need to write reg0x27 0x0001 instead of 0x0100 as shown. So the front-page diagram is not accurate, as it does give the impression that digital gain and offset also apply to the constant mode.

The constant mode does not need trigger. Trigger is for reading through RAM, and digital gain and offset does apply in RAM mode. Since you set reg0x27 to 0x0100 as shown, it is in "RAM" mode. Before you sent trigger, it operates in the default "constant" mode, in which digital gain and offset do NOT apply; and the trigger signal switches it over to RAM mode, in which digital gain and offset DO apply.

Regards,

Will

Hi William,

Thanks for the clarification on this item.

This implies that the Constant mode will be limited to 12 bit if you include both positive and negative range.

If you like to make use of all 14 bit given a static output, would you recommend using a 14-bit value in the SRAM? Optionally with or without the DAC Offset parameter.

The next use case is to slowly (meaning more or less static) looping through all 14-bit values. I see three options. 1) Updating the value in the SRAM 2) Program the SRAM and step the address. Need to be looped a few times. 3) Use fixed value on SRAM and Step the DAC Offset (12 bit). Use 4 values on the SRAM.

Is it some solution you think is preferably compared to the others?

Thanks again for the support.

Regards,
Maritn

Hello Martin,

MartinPe said:

This implies that the Constant mode will be limited to 12 bit if you include both positive and negative range.

Correct.

MartinPe said:

If you like to make use of all 14 bit given a static output, would you recommend using a 14-bit value in the SRAM? Optionally with or without the DAC Offset parameter.

Yest. Although SRAM is also 12bit, so you do need to use digital offset to truly get 14bit.

MartinPe said:

The next use case is to slowly (meaning more or less static) looping through all 14-bit values. I see three options. 1) Updating the value in the SRAM 2) Program the SRAM and step the address. Need to be looped a few times. 3) Use fixed value on SRAM and Step the DAC Offset (12 bit). Use 4 values on the SRAM.

I think #3 will work. The first two won't give you true 14bit as the SRAM is only 12bit.

Regards,

Will

Hi William,

Thanks again.

For the size of the SRAM, could you confirm this? The specification states both 12 and 14 bits (several times).

Best regards,
Martin

The SRAM is 14bit wide as verified by low level SPI controller. Sorry for the inconsistency in data-sheet.

Thanks again for confirming William.

Best regards,
Martin

Oh, and the datasheet said the active bits are <11:0>(12 LSBs), they are actually <15:2>(14MSBs). Again, my apologies for the datasheet error.