AD9162 : minimum reset pulse width for AD9162

Hello,

I got an answer to my previous question.

https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/102024/ad9162-changing-clk-frequency

This answer recommended to be reset after changing the clock frequency.

And I gotten a new question from our customer.
He wants to know minimum width of reset pulse because he need to estimate the transient time from resetting DAC to output new frequency.

Could you tell me the minimum width of reset ?

Best regards,

y-suzuki

  • I probably wasn't clear enough on your previous question: after changing the clock rate, you need to reset THE WHOLE DAC not just the NCO.

     

    To do so, you may do a hard-reset using Reset_N pin of the device or a soft-reset by setting Register 0x000, Bit 0 and Bit 7, and then resetting those bits. The hard-reset is level triggered and as soon as you ground this pin it resets the chip. The soft-reset needs is edge triggered and needs two SPI write actions. So it has enough time in between to perform the reset action.

     

    "Due to internal timing variations from device to deice, these method achieve an accuracy of +/-6 DAC clock cycles"  is talking about the synchronization accuracy of multiple NCOs within multiple chips. It has nothing to do in your case. Please simply ignore it for your application.