I have a critical problem in my PCB and need a urgently help. Please
according to the AD9744's datasheet the input capacitance of a digital pin is 5pF.
as per its IBIS model the DB0 pin in LFCSP package is
now I want to model my PCB in LTspice as follow:
now according to the timing diagram:
I have modeled the problem as follow in LTspice:
when the pos-edge of the DAC_CLK occurs, the first switch (at the input of Cin) is closed and the Cin will be charged. after X nsec (I don't know) the second switch is closed to discharge the capacitor while at the same time the first switch is opened.
now the resistance of the first switch is very important bcoz it can reduce ringing or overshoot of the input signal very effectively.
could you please tell me about the timing and resistance of the input switch?
I have a critical problem in my PCB please help me.