AD9152 DAC PLL Registers

Hi all,

dealing with AD9152 at own board I have find the next problem with DAC PLL initialization.

AD9152 device revision 0x07, DAC REFCLK=250MHz, stable and pure, SPI worked ok, during writing DAC registers according datasheet rev.0 I have seen that some registers return it values not corresponding required in datasheet, for example, the set of registers in Table 17 datasheet (see attached log). As a result the checking register 0x084 say that DAC PLL is not locked.

Registers readback values are shown in the attached file. Is there any ideas what is the problem with this registers and DAC PLL?

Regards,

capt

4336.AD9152_write+verify.txt
AD9152 Configuration

Step 1: Startup the DAC
Power-Up and DAC Initialization according Table 15
Reg[0x000] <= 0xA5  Readback: =0x24 WRITE_VERIFY_FAIL
Reg[0x000] <= 0x24  Readback: =0x24 WRITE_VERIFY_OK
Reg[0x011] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK
Reg[0x080] <= 0x04  Readback: =0x04 WRITE_VERIFY_OK
Reg[0x081] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK
Reg[0x08E] <= 0x01  Readback: =0x07 WRITE_VERIFY_FAIL
Reg[0x1CD] <= 0xD8  Readback: =0xDD WRITE_VERIFY_FAIL

Required SERDES PLL Configurations acc. Table 16
Reg[0x284] <= 0x62  Readback: =0x77 WRITE_VERIFY_FAIL
Reg[0x285] <= 0xC9  Readback: =0x87 WRITE_VERIFY_FAIL
Reg[0x286] <= 0x0E  Readback: =0x08 WRITE_VERIFY_FAIL
Reg[0x287] <= 0x12  Readback: =0x3F WRITE_VERIFY_FAIL
Reg[0x28A] <= 0x2B  Readback: =0x2B WRITE_VERIFY_OK
Reg[0x28B] <= 0x00  Readback: =0x7F WRITE_VERIFY_FAIL
Reg[0x290] <= 0x89  Readback: =0x83 WRITE_VERIFY_FAIL
Reg[0x291] <= 0x4C  Readback: =0x49 WRITE_VERIFY_FAIL
Reg[0x294] <= 0x24  Readback: =0xA0 WRITE_VERIFY_FAIL
Reg[0x296] <= 0x03  Readback: =0x0C WRITE_VERIFY_FAIL
Reg[0x297] <= 0x0D  Readback: =0x00 WRITE_VERIFY_FAIL
Reg[0x299] <= 0x02  Readback: =0x00 WRITE_VERIFY_FAIL
Reg[0x29A] <= 0x8E  Readback: =0xFE WRITE_VERIFY_FAIL
Reg[0x29C] <= 0x2A  Readback: =0x24 WRITE_VERIFY_FAIL
Reg[0x29F] <= 0x7E  Readback: =0x73 WRITE_VERIFY_FAIL
Reg[0x2A0] <= 0x06  Readback: =0x08 WRITE_VERIFY_FAIL

Required DAC PLL Configuration acc. Table 17
Reg[0x08D] <= 0x7B  Readback: =0x7B WRITE_VERIFY_OK
Reg[0x1B0] <= 0x00  Readback: =0xFA WRITE_VERIFY_FAIL
Reg[0x1B9] <= 0x24  Readback: =0x34 WRITE_VERIFY_FAIL
Reg[0x1BC] <= 0x0D  Readback: =0x00 WRITE_VERIFY_FAIL
Reg[0x1BE] <= 0x02  Readback: =0x00 WRITE_VERIFY_FAIL
Reg[0x1BF] <= 0x8E  Readback: =0x8D WRITE_VERIFY_FAIL
Reg[0x1C0] <= 0x2A  Readback: =0x2E WRITE_VERIFY_FAIL
Reg[0x1C4] <= 0x7E  Readback: =0x73 WRITE_VERIFY_FAIL
Reg[0x1C1] <= 0x34  Readback: =0x15 WRITE_VERIFY_FAIL

Optional DAC PLL Configuration acc. Table 18
Reg[0x08B] <= 0x02  Readback: =0x02 WRITE_VERIFY_OK
Reg[0x085] <= 0x08  Readback: =0x08 WRITE_VERIFY_OK
Reg[0x08C] <= 0x02  Readback: =0x02 WRITE_VERIFY_OK
Reg[0x1B6] <= 0x49  Readback: =0x4A WRITE_VERIFY_FAIL
Reg[0x1B5] <= 0x89  Readback: =0x83 WRITE_VERIFY_FAIL
Reg[0x1BB] <= 0x13  Readback: =0x0C WRITE_VERIFY_FAIL
Reg[0x1B4] <= 0x78  Readback: =0x78 WRITE_VERIFY_OK
Reg[0x1C5] <= 0x06  Readback: =0x08 WRITE_VERIFY_FAIL
Reg[0x08A] <= 0x12  Readback: =0x12 WRITE_VERIFY_OK
Reg[0x087] <= 0x62  Readback: =0x62 WRITE_VERIFY_OK
Reg[0x088] <= 0xC9  Readback: =0xC9 WRITE_VERIFY_OK
Reg[0x089] <= 0x0E  Readback: =0x0E WRITE_VERIFY_OK
Reg[0x083] <= 0x10  Readback: =0x10 WRITE_VERIFY_OK
Check for status DAC PLL
 Reg@0x84 =0x00 PLL LOCKDOWN
 Reg@0x8E =0x07

Step 2: Digital Datapath  
Digital Datapath acc. Table 19
Reg[0x112] <= 0x00  Readback: =0x01 WRITE_VERIFY_FAIL
Reg[0x110] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK

Step 3: Transport Layer
Transport Layer Settings acc. Table 20
Reg[0x200] <= 0x00  Readback: =0x01 WRITE_VERIFY_FAIL
Reg[0x201] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK
Reg[0x300] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK
Reg[0x450] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK
Reg[0x451] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK
Reg[0x452] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK
Reg[0x453] <= 0x83  Readback: =0x83 WRITE_VERIFY_OK
Reg[0x454] <= 0x00  Readback: =0x00 WRITE_VERIFY_OK
Reg[0x455] <= 0x1F  Readback: =0x1F WRITE_VERIFY_OK
Reg[0x456] <= 0x01  Readback: =0x01 WRITE_VERIFY_OK
Reg[0x457] <= 0x0F  Readback: =0x0F WRITE_VERIFY_OK
Reg[0x458] <= 0x2F  Readback: =0x2F WRITE_VERIFY_OK
Reg[0x459] <= 0x20  Readback: =0x20 WRITE_VERIFY_OK
Reg[0x45A] <= 0x80  Readback: =0x80 WRITE_VERIFY_OK
Reg[0x45D] <= 0x45  Readback: =0x45 WRITE_VERIFY_OK
Reg[0x46C] <= 0x0F  Readback: =0x0F WRITE_VERIFY_OK
Reg[0x476] <= 0x01  Readback: =0x01 WRITE_VERIFY_OK
Reg[0x47D] <= 0x0F  Readback: =0x0F WRITE_VERIFY_OK

Step 4: Physical Layer
Device Config and Physical Layer Setup acc. Table 21
Reg[0x2A7] <= 0x01  Readback: =0x00 WRITE_VERIFY_FAIL
Reg[0x314] <= 0x01  Readback: =0x00 WRITE_VERIFY_FAIL
Reg[0x230] <= 0x28  Readback: =0x28 WRITE_VERIFY_OK
Reg[0x206] <= 0x00  Readback: =0x01 WRITE_VERIFY_FAIL
Reg[0x206] <= 0x01  Readback: =0x01 WRITE_VERIFY_OK
Reg[0x289] <= 0x04  Readback: =0x04 WRITE_VERIFY_OK
Reg[0x280] <= 0x01  Readback: =0x00 WRITE_VERIFY_FAIL
Check for status SerDes PLL
 Reg@0x281 =0x00 SERDES PLL lockDOWN
 Reg@0x8E =0x07