I am having issues with my SERDES PLL not locking. I follow the setup in the datasheet exactly, my DAC PLL locks, but the SERDES PLL does not. I do not have JESD data connected on my PCB yet, but I was hoping to be able to do some testing beforehand.
Can you confirm where the reference clock for the SERDES PLL comes from? The datasheet and evaluation software is a bit ambiguous:
If the reference is dependant on the DAC Clock, does this then get affected by the JESD m and l settings?
Any help you can give would be very much appreciated.
I have read back all the registers and they (and the pages registers where applicable) match what I expect, and the output of the ACE software memory map.
When I read the SERDES PLL status reg, I get 0x1A => Low overrange, Cal valid, no lock, and interestingly the reserved bit 1, which should be 0, reporting 1.
In my software, when I notice this happening, I force a recalibration (using register 0x280) with a positive edge of bit 2. This doesn't help.
The PLL does sometimes report that it is locked, but immediately falls out of lock.
If the low overrange bit is set that could indicate that the DAC PLL is running with a lower rate than expected. Maybe half of it, that would put the lanerate at ~5.16 GHz, which is just below the lower end of where the SERDES PLL will lock (with your configuration) reliably which could explain why you see it lock and unlock.
Can you share the register settings for the DAC PLL?
The DAC settings are:
Input clock = 128.90625MHz, DAC CLK target = 2062.5MHz; LO Div Mode = 1, Ref Div Factor = 2 (reg value = 1), Fvco is then 8.25GHz. BCount = 16.
Also, PFA a full register dump of the DAC post attempted configuration (p0 is DUAL A and Link 0; p1 is DUAL B and Link 1). All none paged registers are read twice in this.
Your settings look OK. I've tried a similar setup here 128 MHz ref clock, 2.048 GHz DAC clock, 10.24 Gbps lanerate and all PLLs lock.
I'm sure you already checked the external reference clock, made sure that it has the right frequency.
Yes, I am certain my clock is correct.
I have worked out what was going on - we have some ferrite beads with 2Ohms DCR in series on the supply rails. When the device runs, it draws 0.5A through this, causing a 0.4V drop on the supply rail, and browning it out. Removing these fixes it!
Thanks for your help,