I am having issues with my SERDES PLL not locking. I follow the setup in the datasheet exactly, my DAC PLL locks, but the SERDES PLL does not. I do not have JESD data connected on my PCB yet, but I was hoping to be able to do some testing beforehand.
Can you confirm where the reference clock for the SERDES PLL comes from? The datasheet and evaluation software is a bit ambiguous:
If the reference is dependant on the DAC Clock, does this then get affected by the JESD m and l settings?
Any help you can give would be very much appreciated.