I am having issues with my SERDES PLL not locking. I follow the setup in the datasheet exactly, my DAC PLL locks, but the SERDES PLL does not. I do not have JESD data connected on my PCB yet, but I was hoping to be able to do some testing beforehand.
Can you confirm where the reference clock for the SERDES PLL comes from? The datasheet and evaluation software is a bit ambiguous:
If the reference is dependant on the DAC Clock, does this then get affected by the JESD m and l settings?
Any help you can give would be very much appreciated.
The SERDES PLL is using the DAC clock as a reference. When using the internal DAC PLL it will be sourced from it, otherwise the external CLK signal is used.
There are a few SERDES configuration registers that need to be configured according to the chosen lanerate (Mainly 0x230, 0x289).
We have software drivers for both Linux and NoOS that setup the SERDES PLL, maybe that is helpful.
Thanks for your response. Why are all of the config settings to do with the Lane Rate? I could have the same DACCLK with varoius Lane Rates (depending on my JESD setup). Is this allowed, or must my reference clock by Lane Rate / 40?
My reference is 128.90625MHz, and I'm using a 2.0625GHz DACCLK and a Lane Rate of 10.3125Gbps. Is this divided by 40 before going into SERDES PLL? If not, the divide by 4 isn't sufficient to give a valid (35M-80MHz) clock to the PFD?
Is it possible for the SERDES PLL to lock without Serial Data?
I am setting the registers in the same way as the driver you suggested, CDR to 0x28 and PLLDIV to 0x04, as well as all of the constant value registers.
There is an internal clock (in the datasheet referred to as PCLK) that is generated from the DAC clock based on interpolation settings, number of lanes, number of channels, etc. This rate directly correlates with the lane rate and is the input to the SERDES PLL.
The SERDES PLL will lock without serial data.
For the SERDES PLL to lock all the framer settings like number of lanes and number of converters need to be configured correctly. What is your framer configuration?
The settings I am using are:
JESD Mode 6 : M= 2, L = 2, F=2, S=1; K=32, N=NP=16, HD=0, Subclass 0; I'm using all 4 converters in Dual Link Mode.
Interpolation is set to x4.
My PClock should therefore be 257.8125MHz, is that correct? This would then make sense with the Div factor into the SERDES PFD being ~64MHz.
Is there anything that would cause my SERDES PLL not to lock outside of these settings?
Those settings look OK. If you haven't already try to read back all the configuration register you write to make sure that all settings got applied properly.
When you read back the SERDES PLL status register (0x281) check the two OVERRANGE bits, this could help to get an idea what is going wrong.
I have read back all the registers and they (and the pages registers where applicable) match what I expect, and the output of the ACE software memory map.
When I read the SERDES PLL status reg, I get 0x1A => Low overrange, Cal valid, no lock, and interestingly the reserved bit 1, which should be 0, reporting 1.
In my software, when I notice this happening, I force a recalibration (using register 0x280) with a positive edge of bit 2. This doesn't help.
The PLL does sometimes report that it is locked, but immediately falls out of lock.
If the low overrange bit is set that could indicate that the DAC PLL is running with a lower rate than expected. Maybe half of it, that would put the lanerate at ~5.16 GHz, which is just below the lower end of where the SERDES PLL will lock (with your configuration) reliably which could explain why you see it lock and unlock.
Can you share the register settings for the DAC PLL?
The DAC settings are:
Input clock = 128.90625MHz, DAC CLK target = 2062.5MHz; LO Div Mode = 1, Ref Div Factor = 2 (reg value = 1), Fvco is then 8.25GHz. BCount = 16.
Also, PFA a full register dump of the DAC post attempted configuration (p0 is DUAL A and Link 0; p1 is DUAL B and Link 1). All none paged registers are read twice in this.