I am having issues with my SERDES PLL not locking. I follow the setup in the datasheet exactly, my DAC PLL locks, but the SERDES PLL does not. I do not have JESD data connected on my PCB yet, but I was hoping to be able to do some testing beforehand.
Can you confirm where the reference clock for the SERDES PLL comes from? The datasheet and evaluation software is a bit ambiguous:
If the reference is dependant on the DAC Clock, does this then get affected by the JESD m and l settings?
Any help you can give would be very much appreciated.
The SERDES PLL is using the DAC clock as a reference. When using the internal DAC PLL it will be sourced from it, otherwise the external CLK signal is used.
There are a few SERDES configuration registers that need to be configured according to the chosen lanerate (Mainly 0x230, 0x289).
We have software drivers for both Linux and NoOS that setup the SERDES PLL, maybe that is helpful.
Thanks for your response. Why are all of the config settings to do with the Lane Rate? I could have the same DACCLK with varoius Lane Rates (depending on my JESD setup). Is this allowed, or must my reference clock by Lane Rate / 40?
My reference is 128.90625MHz, and I'm using a 2.0625GHz DACCLK and a Lane Rate of 10.3125Gbps. Is this divided by 40 before going into SERDES PLL? If not, the divide by 4 isn't sufficient to give a valid (35M-80MHz) clock to the PFD?
Is it possible for the SERDES PLL to lock without Serial Data?
I am setting the registers in the same way as the driver you suggested, CDR to 0x28 and PLLDIV to 0x04, as well as all of the constant value registers.