AD9144 SERDES PLL Refence Clock

Hello, 

I am having issues with my SERDES PLL not locking. I follow the setup in the datasheet exactly, my DAC PLL locks, but the SERDES PLL does not. I do not have JESD data connected on my PCB yet, but I was hoping to be able to do some testing beforehand. 

Can you confirm where the reference clock for the SERDES PLL comes from? The datasheet and evaluation software is a bit ambiguous:

  • The eval software and the block diagram on p4 of the datasheet implies that the DAC Clock is fed into the SERDES PLL. 
  • Page 37 states that it is 1/40 of the Lane Rate. However, we have not generated this clock yet (or is it taken from the SERDIN inputs?)
  • The f(ref) terminology is also used, which is also used to describe the input CLK. However, there are no constraints on the DAC input clock being linked to the Lane Rate. 

If the reference is dependant on the DAC Clock, does this then get affected by the JESD m and l settings? 

Any help you can give would be very much appreciated.

Thanks,

Henry 

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  • Hi,

    The SERDES PLL is using the DAC clock as a reference. When using the internal DAC PLL it will be sourced from it, otherwise the external CLK signal is used.

    There are a few SERDES configuration registers that need to be configured according to the chosen lanerate (Mainly 0x230, 0x289).

    We have software drivers for both Linux and NoOS that setup the SERDES PLL, maybe that is helpful.

    - Lars

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  • Hi,

    The SERDES PLL is using the DAC clock as a reference. When using the internal DAC PLL it will be sourced from it, otherwise the external CLK signal is used.

    There are a few SERDES configuration registers that need to be configured according to the chosen lanerate (Mainly 0x230, 0x289).

    We have software drivers for both Linux and NoOS that setup the SERDES PLL, maybe that is helpful.

    - Lars

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