Question about the SPI timing spec of AD9116.
1. Could you please let me know the definition of tDV/tDNV using SPI timing chart?
- tDV (SCLK to Calid SDIO)
- tDNV (SCLK to Invalid SDIO)
2. Could you please provide Tr/Tf spec of SCLK/SDIO?
The part was release >10 years ago, so the information in the datasheet is the latest we have at this point.
For SPI, the setup and hold times of DATA relative to SCLK are most critical . Tr and Tf (min rise and fall times) are somewhat less consequential. Faster is likely better, assuming SCLK is 25MHz max.