High-Speed DACs

Q&A

by haerimkim
High-Speed DACs

Latest 11 days ago by haerimkim
210 2 1
Not Answered
AD9175 DAC output problem 0
Not Answered

I am testing a JESD204B-based RF signal chain and observing an unexpected spectrum at the output. My setup is as follows: MPSoC generates a complex sine/cosine waveform using a DDS Compiler IP (1 MHz baseband, sysref = same jesd204b tx_coreclk)...

ad9175 D/A Converters (DAC) hardware jesd204b rf Show More

210 2 1
by kiriuxa
High-Speed DACs

Latest 28 days ago by AlexAtienza
338 6 0
Answered
AD9154 FMC EBZ DAC PLL not being locked when configured through SPI +1
Answered

Hello everyone, I am trying to configure a AD9154 DAC through SPI. The SPI commands are coming from a zynqmp us+ custom board, which is connected to the evaluation DAC board via FMC. The clock signal CLK is also coming from the same board and is configured...

Standard High Speed D/A Converters hardware DAC PLL High Speed D/A Converters =30MSPS clock ad9154 AD9154-FMC-EBZ dac Show More

338 6 0
by UVLSIDRIVER
High-Speed DACs

Latest 28 days ago by AlexAtienza
219 3 0
Answered
Unexpected Noise Band Lift on AD9152 TX2 Using FMCDAQ3 +1
Answered

Hello, We are encountering an issue with the TX output of the AD9152 DAC. Hardware Setup: We are using a custom FMCDAQ3 hardware platform. The FPGA board used is Xilinx ZCU102. Software / Design: We are using the RTL and SDK...

Clock Generation Devices Standard High Speed D/A Converters Clock Generation and Distribution vivado 2018.3 software High Speed D/A Converters =30MSPS sdk 2018.3 fmcdaq3 Show More

219 3 0
by cconrad
High-Speed DACs

Latest 1 month ago by AlexAtienza
137 1 0
Answered
RAMUPDATE and TRIGGER +1
Answered

I'm running into issues with the DAC output stopping. When it stops the only difference is that the PAT_TIMEBASE register (0x28) changes from its default value of 0x0111, seemingly spontaneously, as I do not write to this register. I do write to register...

D/A Converters (DAC) hardware ad9102 AD9102 AD9106 Trigger RAMUPDATE

137 1 0
by hanlilei
High-Speed DACs

Latest 1 month ago by hanlilei
289 4 0
Answered
AD9162 Reset NCO 0
Answered

I'm recently using AD9162, trying to synchronize the output phase of MAIN nco between multiple chips, and confronted by serval problems which i think is not clearly descripted in the datasheet. I tried to use the register bit FTW_LOAD_SYSREF(register...

D/A Converters (DAC) hardware ad9162

289 4 0
by y_suzuki
High-Speed DACs

Latest 1 month ago by y_suzuki
147 2 0
Not Answered
About the power amplifier integrated in AD9166 0
Not Answered

Hello, I have a question about AD9166 from our customer. He wants to know the power amplifier integrated in the AD9166. Could you please tell me which standalone power amplifier most closely resembles the one integrated within the AD9166? Best regards...

D/A Converters (DAC) hardware AD9166

147 2 0
by srujanvedula
High-Speed DACs

Latest 1 month ago by AlexAtienza
254 3 0
Answered
AC/DC Coupling Selection +1
Answered

Greetings. I am designing a signal chain where the analog input can be either DC–10 MHz (DC-coupled) or 100 Hz–10 MHz (AC-coupled) . The signal path is: Input → ADC → FPGA (modulation) → DAC → Analog output I am using the Analog Devices AD9747 DAC...

Standard High Speed D/A Converters hardware High Speed D/A Converters =30MSPS ad9747

254 3 0
by shanghai1
High-Speed DACs

Latest 1 month ago by AlexAtienza
186 3 0
Answered
AD9129 register readback values not matching configuration (especially register 0x33) +1
Answered

I am working with the AD9129 DAC and I'm encountering an issue with register readback after following the startup sequence described in the datasheet. I have configured the device according to the recommended power-up sequence (including SPI setup,...

Datasheet/Specs D/A Converters (DAC) ad9129

186 3 0
by RobertAltmann
High-Speed DACs

Latest 1 month ago by JMMina
127 1 0
Answered
firmware to operate subclass 1 mode for deterministic latency between 2 dac output cannels 0
Answered

i am using the ADS7-V2EZB acquisition board in combination with the AD9174 board to generate two DAC outputs. My aim to to have a deterministic phase difference between the two DAC outputs but that is currenlty not possible. I can only run the boards...

Standard High Speed D/A Converters D/A Converters (DAC) hardware clock and timing ADS7-V2EZB Direct Digital Synthesis (DDS) Show More

127 1 0
by Stefy
High-Speed DACs

Latest 2 months ago by shanghai1
716 7 0
Answered
AD9129 +2
Answered

Hi, I have an AD9129 chip. When I write to register 0x33, I write Data to write =0x13 and read another 0x73. Could you please tell me if this register should be read correctly?

Standard High Speed D/A Converters Datasheet/Specs High Speed D/A Converters =30MSPS ad9129

716 7 0
by adizzz
High-Speed DACs

Latest 2 months ago by adizzz
222 3 0
Answered
Spurs Observed in DAC Output +1
Answered

I am designing a custom board using Zynq-7000 and AD9788 (2EA). Currently, the FPGA Bank is powered at 3.3V , and the DAC data lines are configured as LVCMOS33 . Issue: Significant spurs and noise are observed in the DAC output. Reducing...

Standard High Speed D/A Converters hardware ad9788 High Speed D/A Converters =30MSPS

222 3 0
by Ben3
High-Speed DACs

Latest 2 months ago by PMH2023
318 5 0
Answered
AD9780 / AD9781 / AD9783 Specs: Current noise, Settling Time, Rise Time and Glitch Energy +1
Answered

Looking at the datasheet for the AD9780 / AD9781 / AD9783, I can't find the follow specifications: Output Rise and Fall Time Output-Voltage Settling Time Noise Spectral Density (dBFS/Hz) or Output Noise (pA/rtHz) Glitch Impulse (data says it...

Standard High Speed D/A Converters Datasheet/Specs High Speed D/A Converters =30MSPS ad9780

318 5 0
by prasad@bel
High-Speed DACs

Latest 2 months ago by AlexAtienza
148 1 0
Answered
AD9152 SerDes PLL Reference & DAC PLL Bypass Configuration +1
Answered

I am implementing JESD204B Mode 10 ( M = 1 , L = 1 , S = 1 , F = 2 ) on the AD-FMCDAQ3 with a ZCU102 carrier. Link Configuration: DAC Sample Rate ( F d a c ): 500 MSPS Interpolation: 1x (Data Rate = 500 MHz) Calculated Lane Rate...

Standard High Speed D/A Converters hardware High Speed D/A Converters =30MSPS ad9152

148 1 0
by Ben3
High-Speed DACs

Latest 2 months ago by AlexAtienza
157 1 0
Answered
Is AD9783 Monotonic 0
Answered

Is the AD9783 Monotonic? The datasheet stays the DNL is +/-2 LSB which would make me think not. However, in Table 1, under 'Main Outputs' is a line: 'Main DAC Monotonicity Guaranteed' but that's the label for the row that is empty to right, so it that...

Standard High Speed D/A Converters Datasheet/Specs ad9783 High Speed D/A Converters =30MSPS

157 1 0
by Bill.AvidSystems
High-Speed DACs

Latest 2 months ago by AlexAtienza
319 4 0
Answered
Data Sheet inconsistency +1
Answered

I have a couple questions regarding the Rev C data sheet of the AD9776a DAC. On page 28 register 3 bit 7 shows DATACLK Delay Mode. Page 30 describes this same bit as reserved set to 0. I am guessing that this bit is really the DATACLK Delay Mode bit and...

Standard High Speed D/A Converters Datasheet/Specs High Speed D/A Converters =30MSPS ad9776a

319 4 0

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Q&A

Not Answered
AD9175 DAC output problem 0
Not Answered

Answered
AD9154 FMC EBZ DAC PLL not being locked when configured through SPI +1
Answered

Answered
Unexpected Noise Band Lift on AD9152 TX2 Using FMCDAQ3 +1
Answered

Answered
RAMUPDATE and TRIGGER +1
Answered

Answered
AD9162 Reset NCO 0
Answered

Not Answered
About the power amplifier integrated in AD9166 0
Not Answered

Answered
AC/DC Coupling Selection +1
Answered

Answered
AD9129 register readback values not matching configuration (especially register 0x33) +1
Answered

Answered
firmware to operate subclass 1 mode for deterministic latency between 2 dac output cannels 0
Answered

Answered
AD9129 +2
Answered

Answered
Spurs Observed in DAC Output +1
Answered

Answered
AD9780 / AD9781 / AD9783 Specs: Current noise, Settling Time, Rise Time and Glitch Energy +1
Answered

Answered
AD9152 SerDes PLL Reference & DAC PLL Bypass Configuration +1
Answered

Answered
Is AD9783 Monotonic 0
Answered

Answered
Data Sheet inconsistency +1
Answered

Q&A

Not Answered AD9175 DAC output problem 0 Not Answered

Answered AD9154 FMC EBZ DAC PLL not being locked when configured through SPI +1 Answered

Answered Unexpected Noise Band Lift on AD9152 TX2 Using FMCDAQ3 +1 Answered

Answered RAMUPDATE and TRIGGER +1 Answered

Answered AD9162 Reset NCO 0 Answered

Not Answered About the power amplifier integrated in AD9166 0 Not Answered

Answered AC/DC Coupling Selection +1 Answered

Answered AD9129 register readback values not matching configuration (especially register 0x33) +1 Answered

Answered firmware to operate subclass 1 mode for deterministic latency between 2 dac output cannels 0 Answered

Answered AD9129 +2 Answered

Answered Spurs Observed in DAC Output +1 Answered

Answered AD9780 / AD9781 / AD9783 Specs: Current noise, Settling Time, Rise Time and Glitch Energy +1 Answered

Answered AD9152 SerDes PLL Reference & DAC PLL Bypass Configuration +1 Answered

Answered Is AD9783 Monotonic 0 Answered

Answered Data Sheet inconsistency +1 Answered

Not Answered
AD9175 DAC output problem 0
Not Answered

Answered
AD9154 FMC EBZ DAC PLL not being locked when configured through SPI +1
Answered

Answered
Unexpected Noise Band Lift on AD9152 TX2 Using FMCDAQ3 +1
Answered

Answered
RAMUPDATE and TRIGGER +1
Answered

Answered
AD9162 Reset NCO 0
Answered

Not Answered
About the power amplifier integrated in AD9166 0
Not Answered

Answered
AC/DC Coupling Selection +1
Answered

Answered
AD9129 register readback values not matching configuration (especially register 0x33) +1
Answered

Answered
firmware to operate subclass 1 mode for deterministic latency between 2 dac output cannels 0
Answered

Answered
AD9129 +2
Answered

Answered
Spurs Observed in DAC Output +1
Answered

Answered
AD9780 / AD9781 / AD9783 Specs: Current noise, Settling Time, Rise Time and Glitch Energy +1
Answered

Answered
AD9152 SerDes PLL Reference & DAC PLL Bypass Configuration +1
Answered

Answered
Is AD9783 Monotonic 0
Answered

Answered
Data Sheet inconsistency +1
Answered