In AD9164 Datasheet:
" The SYSREF± signal is sampled by a divide by 4 version of the DAC clock. After SYSREF± is sampled, the phase of the (DAC clock) ÷4 used to sample SYSREF± is stored in Register 0x037,
Bits[7:0] and Register 0x038, Bits[3:0] as a thermometer code. "
If two synchronized CLKs are send to the two AD9164, how to synchronize the "divide by 4 version of the DAC clock" ?
5.b" It is recommended to set SYNC_LMFC_STATx to 0 but it can be set to 4, or a LMFC period in DAC clocks - 4, due to jitter. "
From previous description, writing SYNC_LMFC_STATx is just for saveing the data for readback, the value can be anything.
Why SYNC_LMFC_STATx should be set to those values?