AD9129 Evaluation Board & Xilinx ML-605 Reference Design Questions

Hello Analog Devices

            I’m a physics undergraduate at California Polytechnic and am currently working on the AD9129 Evaluation Board to Xilinx project ( We have all the listed components for the procedure along with a voltage controlled oscillator (Mini-circuits ZX95-2405C-S+, running the DAC as a clock source. This particular oscillator produces a measured output of 2.1 GHz at a power of -1.3dBm. Although this varies slightly from the project description, it should still be an adequate source according to the data sheet for the DAC (

As I understand it, the firmware for the FPGA should produce a digital sine wave with a frequency of 300 MHz, and the AD9129 SPI LabView VI is driving the DAC. When I run the AD9129 SPI program and after programming the FPGA as in the instructions, I observe multiple peaks in the spectrum of the RF output from the DAC space by 65 MHz as shown in the screen shot below. I would expect to see a single peak at 300 MHz.

So far in the testing I've programmed the BIT file through impact and have used the TeraTerm program to connect to the FPGA, setting the baud rate to 57600. Following this process a prompt appears in the terminal which matches what appears on the project page.

The issue I'm having is that the SPI program seems to not have the exact same results as is described. After DLL is disabled and enabled, we receive a broadband noise spectrum with no real distinct peaks besides a small peak about 5 or 10 dB above the noise level. Its frequency changes over time when the PD ALL button is toggled, but settles on a frequency near 355 MHz after a few seconds. After toggling the PD ALL button a few times, I noticed that the settling frequency ranges between ~340 to 360 MHz.

Also, the DLL warning indicator light is switched on. I do not understand the controls on the AD9129 SPI VI, and am at a loss to debug this. Any information or documentation on the “AD9129 SPI” program will be extremely helpful.

I am brand new to using both the Xlinix ML605 and AD9129, so I would appreciate any advice you could give me.

    •  Analog Employees 
    on Feb 15, 2016 7:06 AM

    I am afraid we do not support these interposer designs anymore. However, to give you some pointers, the evaluation board software (the control of the device via the PIC) need to be run first and setup things properly. After you have the DLL tracking locked, you can enable the tone. The tone must be changed to reflect the correct DACCLK.

    If you have regenerated the bit files yourself, double check the buffer locations and make sure they are properly placed (in the same row).

  • Thank you for the response rejeesh, The DLL appears to be locked. But I'm still having some problems with controlling the SPI program.

    How do I verify that everything has been set up properly? Do you mean the registers on the DAC? And the SPI software? What am I looking for?

    What do you mean by changing the tone frequency? Should we be changing this frequency from 300 to 262.5 MHz?

    Also, are there similar interposer designs that are currently supported?

    •  Analog Employees 
    on Feb 23, 2016 7:56 PM


    I moved this to the high speed DAC section - they may be able to help with the SPI/USB programming better than the FPGA team. The FPGA group at ADI no longer support any interposer designs, but the high speed DAC team does.


    •  Analog Employees 
    on Feb 23, 2016 8:11 PM

    Do you have the Quick Start Guide for the evaluation board? That document is installed on your computer in the Programs -> Analog Devices -> AD9129 folder. Please look through it and follow the steps to set up the board. That document also explains each of the tabs in the GUI.

  • I have the quick start guide. It is helpful for me to understand how to get a PLL and DLL lock, even though the face of the GUI I'm working with is different than the screenshots shown in the document.

    But am finding it difficult to follow along since I don't have a DPG2. Where can I purchase one? Do I need a DPG to verify that the board works? Shouldn't the FPGA do the same thing? It should in principle be producing a 300 MHz tone.