The AD9154 specification documents the DAC output phase noise in Figure. 33 (PLL off). A 2.0 GHz DAC clock was externally supplied. Questions
1) What was the phase noise of the 2.0 GHz generator used in this test?
2) Is the observed phase noise limited by the AD9154 or the generator?
2) What is the maximum tolerable phase noise to achieve the performance in Figure 33?
The generator is noted in the figure: SMA100A.
The setup is most likely the same as for the AD9152:
AD9152: Phase Noise Curves and Comparison with AD9912-DDS