AD9102 output signal quality and filtering

Hello together,

at the moment we are busy designing a wide band application using AD9102 produducing a permananet sine wave. With the help of some forum post device now is running.

Setup is fine and frequency and amplitude can easily be adjusted. Requierement is to build a adjustable Sine wave which frequency can be trimed from 4kHz up to 35MHz.

Bassically this works but when I look at the output waveform I am little bit confused concerning output signal quality. Although LVDS is running with 180MHz output of the DDS does not really look like a good sine. Even when a 11,25 MHz sine wave is configuredn it you can easily see quite big resulotion steps. Steps can also be recognized very clear when frequency is set to 1,8 MHz although step size is smaller.

But we need a more smoother output signal where the single steps are not that clear to see.

We thought when using AD9102 with integrated DDS option that there are some signal filter elements are integrated to make a good output signal without having the need to filter externally. This is what we normaly expect when using a DDS and other DDS behave like this.

Of course I can use an external filter for smoothing but before I do this my question:

Is there anything else we have to take into consideration when configuring the device? Is there any chance to influence output quality of the signal or to advice DDS core to make smaller and more steps?

Thanks in advance

Christian

  • Hi -

    Without a filter following the AD9102 output you will see steps in the sinewave output that are more pronounced as you go higher in frequency.

    Thanks

  • Hi Larry,

    ok, that means there is no chance to come along without post filtering. But still I struggle with the quality of the unfiltered output signal.

    In comparsion to other DDS devices it seems as if steps of AD9102 are quite big even if clock input is very high (180MHz) and outfrequency is low (about 10 MHz) to this.

    Is this normal or is there any advice or idea how to reduce step height or an optimum hard- and software configuartion? Does the value of the output resistor and the max. allowed current influence this? At the moment we allow 8mA max. and use 2x124R as out resistor.

    Thanks in advance

    Christian

  • Hi -

    Each sample output should be a flat step. With the AD9102 you can get a better looking step shape by setting the oscilloscope input resistance to 50 ohms.

    Thanks

  • Hi Larry,

    one more question after testing several filter setups.

    If have put a 5th order LC filter at the output of the DDS. Max. output current is set to 8mA so we choose a load resistor of 125R to get an amplitude of 1V.

    That works well if load resistor is 125R per channel. But if a place the additional filter in parallel to termination resistors working on a load impedance this termination resistor reduces so I expect to have an amplitude <1V because max. current is set to 8mA.

    But instead of this there is no output signal at Ioutp and Ioutn anymore. Even if I remove the post filter to have unreduced termination resistor again there is no chance to get an output signal any more. If double checked this with 3 of our PCBs and behaviour stays the same.

    If I use a meter to check the output it seems as if at last one of the output pins are done because measured output resistor is smaller then nominal load resistor of 125R at about 75R.

    If I compare this value to an unmodiefied PCB both output values have the same value of 125R.

    So my questions are the following:

    1. Is observation right that current output can be demaged when load resistor is to small? Does that mean the internal current source is damaged because it has to delivera current >8mA to get an amplitude of 1V?

       If yes where can I find the imoprtant information concerning this issue in the datasheet?

    2. Can you recommed an optimal load resistor and post filter setup for that device?

       I have seen that nominal value at the evalutaion board is 250R per Iout channel but we cannot use transformes to adjust  

       to an specific load and filter due to space problems. The only chance ist to use LC filters

    What can we do or test  to solve the problem?

    Thanks in advance

    Christian

  • Hi -

    Table 9 of the data sheet tells you that IOUTP and IOUTN cannot exceed AVDD + 0.3V. Voltages significantly higher that that can damage the AD9102 output circuit. You should make sure the voltage at IOUTP and IOUTN is between -0.3V and AVDD + 0.3V.

    Thanks