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Clear NCO phase on SYSREF edge (AD9172)

 Dear All!

I have a problem in reset NCO phase of all channel ( include channel data path, main data path, 2 DAC) synchronize with sysref   signal. Current mode used is :

    + JESD 204b. Subclass1. Mode1, Dual channel.

    + Sysref 1MHz continuous pulse,50% duty cycle

    + DAC freq : 9216 MHz

    + Channel_NCO freq : 1152 MHz

    + Board : AD917x-FMC-EBZ

    + Sysref :On, AC mode

As in data sheet, NCO can reset by sysref signal by setting bit 2 in register 0x131 for channel NCO and 0x113 for main NCO. But no thing happened. Is any setting need for auto reset NCO with sysref signal????

  • Hi Hoang,

    I'd need to check regarding NCO reset specifically, but in terms of SERDES clock alignment, the alignment to the SYSREF pulse is a "one shot" process, done just once at link startup. Subsequent SYSREF pulses are ignored unless you restart the one-shot sync.

    Just to make sure, do you get an NCO tone in subclass0 for the same setup and conditions?Is the issue only with resetting the NCO on every subsequent SYSREF pulse (post JESD204B link establishment)?

    Best Regards,


  • Dear Arik!

    My issue is only about resetting the NCO on every subsequent SYSREF pulse. When change NCO FTW and perform load by toggle bit0 in register 0x131 and 0x113 (SW update by SPI write), start phase at next period is changed. I need reset it sync with sysref so that each DAC channel can maintain some fixed startup phase .

    Best Regards!


  • Hi Hoang,

    Apologies for the delay. bit2 should function as expected, setting the AD917x NCO to update the FTW (reset) on the next rising edge. 

    Can you reset the NCO using the SPI register?

    How do you know that nothing happens when a SYSREF pulse is detected? 

    Best Regards,


  • I am having a similar problem.  I want to resync the main NCO to the SYSREF clock.  My test setup is running  on the EVB.  I have programmed the HMC7044 to pass a 100 MHz reference through from J41 to the AD9172 for use as SYSREF.

    This same 100 MHz is used as the reference for a signal generator running at 5 GHz.  The generator is used as an external DAC clock.

    I am looking at both the 100 MHz reference and the NCO output, which is also set to 100 MHz, on an oscilloscope.  After initial startup there is a finite phase offset between these two signals.  If I reprogram the NCO to be the same frequency the phase difference is random.

    The description in the data sheet for register 0x1E7 bit zero is unclear.  It says that setting it to a 1 will start the resync based on either the SPI bit or the SYSREF rising edge.  Which register setting is used to select the SPI or SYSREF as the trigger source?