I am trying to obtain deterministic latency between the AD9164 and a Xilinx UltraScale+ FPGA using the Xilinx JESD204B core. I can establish a link between the devices and reliably transfer data, but the latency through the device changes from POR to POR. Note I am running both the DAC and Xilinx Core in Continuous sync mode. The JESD interface is configured as follows.
Data rate: 4.8GHz
Lane rate: 12GHz
PCLK rate: 300MHz
Frame rate: 1.2GHz
L = 8
F = 1
S = 4
I believe that my clock relationships are correct and that I am meeting the Setup/hold requirements for SYSREF but I cant see the clocks right at the part. I can only observe at the PLL generating both DCLK and SYSREF clocks. Is there anyway to verify using registers inside the part?
To measure the latency through the interface, I have a data generator inside the FPGA that I am using to generate a 300MHz sine wave. Until enabled, the data generator outputs zeros and when enabled generates a 300MHz sine wave. The enable used to start the generator is output with the data and I am using it to measure the delay from the start of data transmission into the JESD transmitter until the data is output from the DAC. I am also reading the the SYSREF_PHASEx and SYNC_LMFC_STATx registers with each transfer. These are the latencies I am seeing from POR to POR and the SYSREF_PHASE for each:
SYSREF PHASE Delay
Sorry for the delay. In the meantime, we are working on a procedure to use the SYSREF phase information to guide in the delaying of the LMFC at the source (FPGA). This is a project we are working on as we have time. IF you have further information from the FPGA side, let us know.
If after multiply POR cycles the Dynamic Link Register reports every possible latency between the LMFCrx and the LMFC aligned to SYSREF what is this telling me? What would cause the Dynamic Link Latency to take on every possible delay?