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How to configure AD9162 to meet JESD204B subclass-1 deterministic latency from POR to POR?

We need the AD9162, post every power-on-reset/initialization (POR), to output a waveform with the same deterministic delay with respect to an external trigger that’s phase coherent (fixed phase-relationship) with respect to the DAC’s SYSREF and sample clock; but are unable to do so. Our question therefore is how to accomplish this?

According to:, slide 20: The JESD204B specification defines Deterministic Latency as the time difference between (Tx frame & Rx de-frame) the frame based data generation at the Tx to when the frame based data on Rx is output measured within the Frame Clock domain. The specification further specifies that the deterministic latency shall be programmable in increments at least as small as the Frame Clock period, and shall be repeatable from power-up cycle to power-up cycle, AND shall be repeatable regardless of link resynchronization events. This video is incomplete, it would be nice to provide a link to its entirety.

According to caption of Table 23 on pg. 54 AD9162 datasheet (Rev. C), SYSREF is sampled with an internal divided by 4 version of the DAC clock. Therefore, unless this divided-by-4 is synchronously reset from POR to POR there are four possible phase states. Hence, under Subclass 1 description on the same page: this mode gives deterministic latency and allows the link to be synced to within four DAC clock periods.  However, step-6 of the Sync Procedure on the same page provides a means to read back the SYSREF_PHASEx register to identify which phase of the divide by 4 was used to sample SYSREF. According to the answer provided by, doing so would produce a synchronization accuracy in a multi-convertor case within a single DAC clock cycle. We are simply trying to accomplish such accuracy for a single convertor case from POR to POR.

We have an external SYSREF signal that is accurately phase aligned to the DAC clock. The SYSREF and Device Clock signals are also POR deterministic with respect to the core clock/SYSREF fed to the JESD204B transmitter IP of the FPGA. Our settings are: M=1, L=8, F=1, SYNCMODE = Continuous, No SYNC errors were reported, DAC’s internal PLL locked every time without issue.

We also followed procedures on pg. 56 for Link Delay Setup Example, Without Known Delay. However, we see up to 8 PCLK variations from POR to POR relative to the synchronous external trigger. Such variations are >> 4 DAC clock cycles. We have gone through pertinent sections of the DAC datasheet to no avail, and would much prefer an offline real-time person-to-person discussion.

  • I was trying to find the DAC clock rate and also interpolation factor that you are using for this experiment but nothing was mentioned regarding these parameters in your post. I hope you can provide more detailed information regarding the DAC configuration.

    As far as I can tell and as advertised in our datasheet and proven by different experiments we've carried out on this device, in subclass-1 mode, the deterministic latency from POR to POR falls within 4x DAC clock cycles. This is valid unless you read back SYSREF_PHASEx registers and try to rotate clocks in order to achieve latency within 1x DAC clock cycle.

    I would be more than happy to help you out to resolve the issue but need more information on your setup.