Output sawtooth wave to AD9144

This is a question about the operation of the AD9144.
My customers are evaluating the AD9144.
My customer is trying to output sawtooth waves from AD9144.
T = 200 nS, + 100 count → -100 count
The customer inputs the code and evaluates the output waveform.
Strangely, the output slope bounces small around 0 count.
Customers suspect this as miscounts.
Is this due to the nature of T-DAC?
Do you have any views?
Please advise me.

 

Is this phenomenon called MIDSCALE GLITCH?
Where should I check to isolate it from mistakes in circuit design?

Best regards

  • Hi

    I upload vector data.
    This is data of T = 200 nS, + 100 count → -100 count.

     

    I confirmed to the customer, the phenomenon is going on the customer's board.
    I encourage customers to monitor digital supplies.

     

    Best regards

    data.txt.zip
  • Hi Mochi,

    My guess is the issue is related to the point in the vector where all 1's trnsition to all 0's.

    likely a load regulation issue on the digital supply. Consider checking the digital supplies during the transition on a scope, comparing against the DAC output: it is possible the issue is simply to the available charge during the transition, in which case adding a bulk capacitance (say 10-20uF) near the DAC could help.

    If a scope isn't available, an interesting test would be to compare data vectors that are 2's complement vs. unsigned. In this case the glitch should move by a few samples. The data format is configurable at the AD9144:

    this would simply confirm the issue, not fix it.

    Was the issue noted on an AD9144 EVB, or was it on the customer's board?

    Best Regards,

    Arik

  • Hi

    My customers confirmed the power supply with an oscilloscope, but they say that they can not find fluctuations synchronized with the glitch.
    The power supplies they have confirmed are AVDD33, PVDD12, CVDD12.DVDD12, SVDD12 (VTT), IOVDD (SIOVDD33).
    They said that they were monitored at both ends of the capacitor furthest from the power supply regulator.

    The circuit of the power supply regulator follows FMCDAQ2.
    Each system of 3.3 V and 1.2 V system is supplying power to each terminal of DAC through LPF (chip bead and 4.7 μF capacitor).

    They are saying to try adding capacitors to the power supply system.

     

    By the way, I'm wondering, can the glitches shown by customers be found on the evaluation board with meticulous observations?
    Also, if they evaluate the output waveform in the frequency domain, is it likely to be a problem?

     

     

     

    Best regards

  • Hi mochi,

    I'd suggest for you to get an EVB to try this on. The customer may benefit from one long-term as well, to compare against their own board.

    We had never noticed any INL/DNL issues of this kind during development, not on the EVB either. The issue is likely on the customer board, with the layout, power supply section, or the vector. 

    Have you tried switching between 2's comp and unsigned vectors?

    Do you generate the vectors using DPG Downloader?

    Best Regards,

    Arik

  • Hi
    My customer confirmed this matter using EVB.
    Please see the attached file.

    My customers claim that something similarly occurs in the EVB.
    When I posted, the customer had trouble in controlling the FPGA.
    Now the customer overcomes the trouble, the EVB and customer's board are using the same input procedure.

    I am asking customers to evaluate in the frequency domain.
    However, there are no results yet.
    Please let me know your view on something.

    Customers also care about crosstalk.
    This is crosstalk coming from other channels of the AD9144.
    Please also tell me about your opinion about this.

    I apologize to you for 2's comp and DPG Downloader that it is not progressing.
    I would like to know about 2's comp and DPG Downloader.

    Best regards

    attachment.pdf