Post Go back to editing


I catch the sync signal in chipscope(tx_core_clk domain)show below.The SYNC signal from the AD9173 has been periodically dropped.

PS:My transmitter clock is not synchronization with the ad9173 device clock,is there  something wrong with that?

Parents Reply
  • Hi 

           I finally achieved JESD synchronization and the issue ended up being on the FPGA side. I tested it on Xilinx FPGA. According to the IP specification, tx_core_clk = Lane rate / 40, but I set it wrong before. Thanks a lot!

         However, when it works normally, I check that DLL_Lock(0x0C3 BIT0) and NVM_ Blrdone(0x705 BIT1) are still pulled down.  In the first time according to the start-up sequence configuration is pulled high.Is there something wrong with that?

  • Hi SAli486,

    That is great news ! However, issues with the DLL lock registers usually come up from an error in the startup sequencing. Please make sure to follow the startup sequence as listed in table 49 to table 58 in the data sheet. In addition, make sure that the registers are configured correctly according to your system parameters  (i.e interpolation, JESD lanes, fdac, clock, etc.) Otherwise, it might give you unexpected results that do not match the correct configuration. I hope this helps.

    Best regards,