After I configured the AD9173, the DLL and SERDES PLL are locked normally. When the JESD204B link is established, the SYNC signal keeps dropping periodically. I read back through the registers 0X470 = FF and 0X471 = FF, 0X472 = 00; so I can locate that the link reconnection is caused by this step of CHECKSUM.
But through the datasheet I can see that the check values are equal to DID = 0, BID = 0, LID = 0, SCR = 0, L-1 = 7, F-1 = 0, K-1 = 31, M-1 = 1 , N-1 = 10, SUBCLASSV = 1, NP-1 = 15, JESDV = 1, S-1 = 1 and HD = 1 are accumulated and divided by 256 to take the remainder; should be CHECKSUM = 44. I write this value to the register 0X45D (Is this correct?).
Mode 15 of my JESD204B mode selection: L = 8, N = 11, NP = 16, S = 2, K = 32, F = 1, M = 2. My DAC sampling clock is 2.25G and lane rate = 11.25G.
In addition, I want to know if this step of CHECKSUM is related to the IP core configuration of JESD204b on the FPGA side.
This problem has troubled me for many days, please give me some directions or suggestions.
