The SYNC signal of the JESD204B of the AD9173 has been periodically dropped.

Have you solved the problem? I had the same problem.

Dear saqib,

Your transmitter and AD9173 clock should be a match in order for the JESD204B link to be synchronized. Most of these errors are a result of clocking issues or the physical connection between the devices.  Make sure both the CLKIN for the DAC and the refclk for the FPGA are the exact appropriate frequency.  You can also refer to our JESD204B Debug guide for more tips. I would refer to slides 22- 34 for your issue in terms of startup and synchronization.

https://www.analog.com/media/en/training-seminars/tutorials/JESD204B-link-debug.pdf

Best regards,

Zaid 

Thanks for your reply, I also saw the documentation you provided is great for debugging 204B.

   The problem has been solved, here to tell everyone the reason, hope to help others

   When the 204B link was established, the serdes pll was locked, the K code verification was completed, and the ILAS frame transmission could also be completed, but the checksum failed, resulting in the link being reestablished continuously.This proves that the parameters in ilas are wrong, but I have carefully checked for a long time and found that the parameter configuration is not wrong. In the end, I found that there are few parameters in the gt0 ~ 7_rxdata and gt0 ~ 7_rxcharisk signals that are monitored using ila in the 204B core of FPGA It is the glbclk clock and data_reg wiring in the FPGA that are too scattered, resulting in data confusion, and the problem is solved after constraining the location of FPGA data_reg to around gtx io.

Hello, I also encountered this problem, can you send me  this XDC file for constraining the location of FPGA data_reg to around gtx io?