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The SYNC signal of the JESD204B of the AD9173 has been periodically dropped.

   After I configured the AD9173, the DLL and SERDES PLL are locked normally. When the JESD204B link is established, the SYNC signal keeps dropping periodically. I read back through the registers 0X470 = FF and 0X471 = FF, 0X472 = 00; so I can locate that the link reconnection is caused by this step of CHECKSUM.

   But through the datasheet I can see that the check values are equal to DID = 0, BID = 0, LID = 0, SCR = 0, L-1 = 7, F-1 = 0, K-1 = 31, M-1 = 1 , N-1 = 10, SUBCLASSV = 1, NP-1 = 15, JESDV = 1, S-1 = 1 and HD = 1 are accumulated and divided by 256 to take the remainder; should be CHECKSUM = 44. I write this value to the register 0X45D (Is this correct?).

   Mode 15 of my JESD204B mode selection: L = 8, N = 11, NP = 16, S = 2, K = 32, F = 1, M = 2. My DAC sampling clock is 2.25G and lane rate = 11.25G.

   In addition, I want to know if this step of CHECKSUM is related to the IP core configuration of JESD204b on the FPGA side.

   This problem has troubled me for many days, please give me some directions or suggestions.


  • Have you solved the problem? I had the same problem.

  • Dear saqib,

    Your transmitter and AD9173 clock should be a match in order for the JESD204B link to be synchronized. Most of these errors are a result of clocking issues or the physical connection between the devices.  Make sure both the CLKIN for the DAC and the refclk for the FPGA are the exact appropriate frequency.  You can also refer to our JESD204B Debug guide for more tips. I would refer to slides 22- 34 for your issue in terms of startup and synchronization.

    Best regards,


  • Thanks for your reply, I also saw the documentation you provided is great for debugging 204B.

  •    The problem has been solved, here to tell everyone the reason, hope to help others

       When the 204B link was established, the serdes pll was locked, the K code verification was completed, and the ILAS frame transmission could also be completed, but the checksum failed, resulting in the link being reestablished continuously.This proves that the parameters in ilas are wrong, but I have carefully checked for a long time and found that the parameter configuration is not wrong. In the end, I found that there are few parameters in the gt0 ~ 7_rxdata and gt0 ~ 7_rxcharisk signals that are monitored using ila in the 204B core of FPGA It is the glbclk clock and data_reg wiring in the FPGA that are too scattered, resulting in data confusion, and the problem is solved after constraining the location of FPGA data_reg to around gtx io.



  • Hello, I also encountered this problem, can you send me  this XDC file for constraining the location of FPGA data_reg to around gtx io?