Question: What is the maximum trace length allowed for output signals from AD9739 prior to the RF transformer? Resolution: The recommendation is that the RF transformer is placed as close to the DAC outputs…
Question Since AD9739 supports input data rates from 1.6 GSPS to 2.5 GSPS using dual
LVDS data ports, what host processor can we use to send data to AD9739 and how
to connect the host processor for…
Question I am interfacing two AD9739 DAC's with VIRTEX-5. In the datasheet of AD9739 at
PAGE NO. 49 under the section of INTERRUPT REQUESTS, it is given that --"If the
pin is used to determine that…
Question I'm going to use two parts into a board, and the sampling clocks for both DACs
are sourced by the same clock distribution module. So the synchronization is
inherent to the system architecture…
Question I have an application which require the two DAC's output phase difference
should be smaller than 3 degree, If I use design synchronization circuit shown
in Figure 1, and DACLCK is 1GHz, AD9739…
Question I'm driving a AD9739 DAC from a Virtex-5 FPGA and I have a question about the
LVDS inputs.
I'm having problems with locking of the data receiver and I'm thinking that
this may be because…
Question In ref schematic for DAC AD9739 MIX MODE OUTPUTS are connected to secondary
of BALUN MABACT0039 while for normal mode it is connected to primary of baloon.
What is the difference? Answer The…
Question I used ADCLK914 to drive the DACCLK according to description mentioned in the
datasheet. However, I found when AD9739's clock pins are connected to CLKP and
CLKN, there seemed to be a voltage…
Question My application requires a wideband, single-ended, 50 Ohm output (20MHz -
2.5GHz). I was thinking to use the output stage as implemented on the
evaluation board (AD9739_R2-EBZ EVALUATION BOARD…
Question In brief, in one of running research projects we require a solution where we
record an analogue baseband (NOT RF) signal with a bandwidth of about 100 MHz
and later we 'replay' this signal…