Question: Why is there power supply decoupling between VDDA25 and VNEG12 on the AD9162 eval board? And what is the purpose of the SA_GND? Answer: The DAC core swings between VDDA25 and VNEG12, so decoupling…
Question: Is there a partial/minimal start-up sequence that would allow SW to read the CODE_REF register but keep the rest of the DAC in a low power mode so the DAC’s self-heating is minimized? Resolution…
Question: Do you have a user’s guide for creating chirp waveforms using the AD9164 with the pattern generator board?
Resolution: There is no documentation on the chirp generator in DPG Downloader. The…
Question: Is there an IBIS-AMI model for AD9162? If not, is there an existing IBIS-AMI model for a similar package / device that can be used to simulate the JESD204B interface? Resolution: No, there is…
Question: Can I mux the data over the JESD204B interface like the following: ASIC to use lanes 4-7, and FPGA to use lane 0-3 or vice versa? Resolution: No, Lane 0 must used whenever SERDES data is needed…
Question: The external clock input on the AD9164-FMC-EBZ isn't working. ACE software selects to change it, but nothing happens on the eval board. Resolution: This is a known issue with boards that were…
Question: I am using the AD9163-FMCC-EBZ and ADS7-V2. How do I generate signals as I want (sines with different freqs. combinations) using the ADS7-V2 software? Can I use my own application (labview, matlab…
Question: If I change the DACCLK on the AD9164 when using it as a DDS , what is the recovery time? How fast can I change sample clock and tuning word? Answer: The part would need to re-lock the DAC clock…