How does the AD9625 timestamp sampled data?

How does the AD9625 timestamp sampled data?

The AD9625 can use the SYSREF± pins in either of 2 modes: LMFC alignment for JESD204B subclass 1 or as a timestamp mode to append a marker to a particular sample.

The SYSREF± pins in the AD9625 can be used as a timestamp of data as it passes through the ADC and out the JESD204B interface. The timestamp marker will have the same pipeline latency as the analog sample that is coincident with the same encode clock. This is accomplished by the use of the extra output JESD204B control bits to insert the synchronous low to high captured SYSREF± signal. These extra control bits are only available while in the JESD204B generic 2, 4, and 8 lane modes.  These modes provide extra auxiliary bits as they use JESD204B parameters of N'=16 and N=12.

Please reference the attached document for a complete reference on the feature.

Other links to this topic:

Demystifying Deterministic Latency Within JESD204B Converters | Analog content from Electronic Design

JESD204B Subclasses (part 1): Intro and Deterministic Latency | EDN

JESD204B Subclasses (part 2): Subclass 1 vs. 2, System Considerations | EDN


Thanks,

Ian Beavers

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Anonymous
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    •  Analog Employees 

    Hi Trevor-

    Let's start with your description of the 16b data partitioning that you mention, which is correct:

    {12-bits of data, Over-Range, SYSREF, C2, C3}

    C0 is the over-range bit as you describe. C1 is SYSREF.  C2 and C3 are not used for any meaningful data on AD9625.

    There are a couple of areas in the datasheet where this is mentioned, but it may not be 100% clear.
    Based on the JESD204B specification of the control bits, CS=1 means that the control bit information must be placed after the N bits of ADC data, which in this case is 12b out of the 16b JESD204B sample. The over-range bit comes out in bit [3] of the 16b JESD204B sample, where the top 12b are the ADC output
    data.  So, this is the bit after the LSB.  As you mention, the SYSREF indicator bit is in bit location [2].  Bits [1] and [0] of the 16b sample are not used in any case.  For the SYSREF control bit enable case, it can only also be enabled with the over-range control bit.  It cannot be enabled on its own (as seen in table 73 below).

     

    Thanks,

    Ian Beavers

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    •  Analog Employees 

    Hi Trevor-

    Let's start with your description of the 16b data partitioning that you mention, which is correct:

    {12-bits of data, Over-Range, SYSREF, C2, C3}

    C0 is the over-range bit as you describe. C1 is SYSREF.  C2 and C3 are not used for any meaningful data on AD9625.

    There are a couple of areas in the datasheet where this is mentioned, but it may not be 100% clear.
    Based on the JESD204B specification of the control bits, CS=1 means that the control bit information must be placed after the N bits of ADC data, which in this case is 12b out of the 16b JESD204B sample. The over-range bit comes out in bit [3] of the 16b JESD204B sample, where the top 12b are the ADC output
    data.  So, this is the bit after the LSB.  As you mention, the SYSREF indicator bit is in bit location [2].  Bits [1] and [0] of the 16b sample are not used in any case.  For the SYSREF control bit enable case, it can only also be enabled with the over-range control bit.  It cannot be enabled on its own (as seen in table 73 below).

     

    Thanks,

    Ian Beavers

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