How does the AD9625 timestamp sampled data?
The AD9625 can use the SYSREF± pins in either of 2 modes: LMFC alignment for JESD204B subclass 1 or as a timestamp mode to append a marker to a particular sample.
The SYSREF± pins in the AD9625 can be used as a timestamp of data as it passes through the ADC and out the JESD204B interface. The timestamp marker will have the same pipeline latency as the analog sample that is coincident with the same encode clock. This is accomplished by the use of the extra output JESD204B control bits to insert the synchronous low to high captured SYSREF± signal. These extra control bits are only available while in the JESD204B generic 2, 4, and 8 lane modes. These modes provide extra auxiliary bits as they use JESD204B parameters of N'=16 and N=12.
Please reference the attached document for a complete reference on the feature.
Other links to this topic:
JESD204B Subclasses (part 1): Intro and Deterministic Latency | EDN
JESD204B Subclasses (part 2): Subclass 1 vs. 2, System Considerations | EDN
Thanks,
Ian Beavers
Top Comments