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Documents AD6676 What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
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    • I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?
    • Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
    • What determines the AD6676’s full-scale input setting?
    • What is the STF response of a Σ-Δ ADC and why does it matter?
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    • AD6676 What development tools are available?
    • AD6676 What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
    • AD6676 Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?
    • AD6676 Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
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    • AD6676 I heard that Σ-Δ ADC’s can be driven into overload resulting in unstable behavior.  Is this true and should I be concerned?
    • Operating AD6676 at Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
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AD6676 What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?

An IF-sampling ADC typically refers to any ADC capable of digitizing an IF signal in its 2nd Nyquist zone (or higher) while still achieving sufficient dynamic range for the target application.   In a heterodyne or direct-sampling VHF receiver architecture, the IF-sampling ADC is just one of several components required in the IF strip to complete the signal chain.  Other components in support of the IF-strip may also include an IF SAW filter, digital-gain-amplifier, L-C “roofing” filter, ADC buffer amp, and clock generation IC. 

The AD6676 is called a wideband IF receiver subsystem because it integrates much of this functionality into a small 4.3mm x 5.0mm WLCSP package allowing it to directly interface to an RF-to-IF mixer via a simple low order L-C “roofing” filter resulting in considerable PCB area savings.   The continuous-time band-pass Σ-Δ ADC operates up to 3.2 GSPS thus “oversampling” the IF signal while providing very high dynamic range (NSD as low as -160 dBFS/Hz).  This attribute eliminates the need for an IF SAW filter (and subsequent IF gain stage) that serves as an aggressive anti-aliasing filter for a typical IF-sampling architecture.    Additionally, its low full-scale input power of -2 dBm (or less) allows considerable headroom to use its on-chip digital attenuator for AGC or level planning purposes.   In fact, RF-IF component line-ups operating off a 3.3 V supply become feasible (along with power savings) since the P1dB requirements of these components can be relaxed.  Digital integration also includes a QDDC with selectable digital decimation filters to provide 16-bit I/Q data transferred to the host over a JESD204B interface. Additional digital features facilitate fast AGC control, fast TDD power-down savings modes, and the ability of the Σ-Δ ADC to be quickly reconfigured in under 1 µsec to four different IF and bandwidth settings.  

In summary, the AD6676 is a re-configurable wideband IF receiver system that can enable some of the smallest, yet highest AGC-free dynamic range heterodyne or direct-sampling VHF radio receivers in the industry.

 

For more information, visit the AD6676 product page.

Tags: wideband_if high_speed_converter ad6676 high_speed_adc if_sampling_adc wideband_if_receiver_subsystem high_speed_analog_to_digital_converter Show More
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