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High-Speed ADCs
  • Data Converters
High-Speed ADCs
Documents What determines the AD6676’s full-scale input setting?
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High-Speed ADCs requires membership for participation - click to join
  • HIGH-SPEED ADC SUPPORT COMMUNITY
  • TAGS LIST: High-Speed ADCs
  • +Absolute Group Delay: FAQ
  • +AD6620: FAQ
  • +AD6624A: FAQ
  • +AD6633: FAQ
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  • -AD6676: FAQ
    • I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?
    • Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
    • What determines the AD6676’s full-scale input setting?
    • What is the STF response of a Σ-Δ ADC and why does it matter?
    • AD6676 FAQ: Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?
    • AD6676 FAQ: What development tools are available?
    • AD6676 FAQ: What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
    • AD6676 FAQ: Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?
    • AD6676 FAQ: Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
    • AD6676 FAQ: Why isn't the noise floor of the AD6676 flat?
    • AD6676 FAQ:I heard that Σ-Δ ADC’s can be driven into overload resulting in unstable behavior.  Is this true and should I be concerned?
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  • +JESD204B: FAQ

What determines the AD6676’s full-scale input setting?

To a first order, the full-scale setting (PIN_0dBFS) is given by the following equation with IDACIFS being the full-scale current setting of the 1st stage feedback DAC and  RIN being the IF input resistance.

 

PIN_0dBFS = 10 × log10(1/2 × RIN × IDAC1FS2)

 

IDACIFS can be varied over a 4 to 1 mA range thus allowing PIN_0dBFS to be varied over a 12 dB range. At the max setting of 4 mA and an RIN of 60 ohms, the theoretical PIN_0dBFS is -3.2 dBm.  In practice, the IF, FADC, and Lext settings have a secondary affect that may result in the PIN_0dBFS being up to 1 dB higher than the theoretical value.

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