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High-Speed ADCs
Documents AD6676 FAQ: Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
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  • HIGH-SPEED ADC SUPPORT COMMUNITY
  • TAGS LIST: High-Speed ADCs
  • +Absolute Group Delay: FAQ
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  • -AD6676: FAQ
    • I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?
    • Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
    • What determines the AD6676’s full-scale input setting?
    • What is the STF response of a Σ-Δ ADC and why does it matter?
    • AD6676 FAQ: Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?
    • AD6676 FAQ: What development tools are available?
    • AD6676 FAQ: What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
    • AD6676 FAQ: Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?
    • AD6676 FAQ: Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
    • AD6676 FAQ: Why isn't the noise floor of the AD6676 flat?
    • AD6676 FAQ:I heard that Σ-Δ ADC’s can be driven into overload resulting in unstable behavior.  Is this true and should I be concerned?
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AD6676 FAQ: Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?

While the design target was 50 ohms, device characterization for several lots has shown it to be closer to 60 ohms.  That said, operating with a low IF input resistance reduces PIN_0dBFS of the AD6676.  This in turn can reduce the P1dB requirements of the device driving the AD6676 thus allowing it to operate at lower supply level (i.e. 3.3 V vs 5.0 V) as well as at reduced power consumption.   Alternatively, the lower PIN_0dBFS can be used to extend the IF AGC range where the P1dB of the device driving the AD6676 (i.e. mixer) often sets the upper limit.

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