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Documents AD6676 Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?
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  • HIGH-SPEED ADC SUPPORT COMMUNITY
  • TAGS LIST: High-Speed ADCs
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    • I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?
    • Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
    • What determines the AD6676’s full-scale input setting?
    • What is the STF response of a Σ-Δ ADC and why does it matter?
    • AD6676 Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?
    • AD6676 What development tools are available?
    • AD6676 What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
    • AD6676 Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?
    • AD6676 Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
    • AD6676 Why isn't the noise floor of the AD6676 flat?
    • AD6676 I heard that Σ-Δ ADC’s can be driven into overload resulting in unstable behavior.  Is this true and should I be concerned?
    • Operating AD6676 at Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
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AD6676 Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?

This feature can be useful for applications that may desire to cover a larger IF bandwidth range but do not necessarily need the instantaneous bandwidth.  By dividing the larger IF bandwidth into  narrower “sub-bands” , it is possible to increase the Σ-Δ ADC’s dynamic range for each “sub-band” versus one Σ-Δ ADC setting that tries to cover the entire IF bandwidth.  Recall that the dynamic range of a Σ-Δ ADC is a strong function of its oversampling ratio (i.e.  OSR= FADC/(2*BW)).

This feature allows the Σ-Δ ADC to store up to four different profile settings that can be quickly recalled within 1 µs via a SPI command without recalibrating the Σ-Δ ADC. Calibration of each of the different profiles occurs during the device initialization phase with each profile consisting of the following different application parameters: BW, FIF, IDAC1FS, and MRGN.   To ensure that the JESD204B link is maintained when switching between profile settings, the FADC setting along with the decimation filter and JESD204B settings must remains common.

Figure91. NSD Performance with Narrow-Band Profiles (FIF = 220 MHz, 260 MHz, and 300 MHz, BW = 120 MHz, FADC = 3.2 GHz, LEXT = 27 nH)

For more information, visit the product page.

Tags: wideband_if ad6676 sigma_delta_adc high_speed_adc high_speed_ad_converter high_speed_converters jesd204b wideband_if_receiver_subsystem high_speed_analog_to_digital_converter Show More
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