A Σ-Δ ADC employs negative feedback to reduce the noise contribution of its internal quantizer. The quantizer in any ADC can be driven into overload under large signal conditions, causing its output to be a poor representation of its input. However, unlike traditional ADCs that operate in open-loop, a Σ-Δ ADC can be driven into overload with signals below its 0 dBFS full scale input level and the feedback loop can become unstable. It is worth noting that an overload event is dependent on the waveform characteristics, with a CW waveform representing worst case since input levels near its peak have the highest probability of occurrence compared to a band limited AM/PM modulated waveforms.
The AD6676 employs several techniques to solve this problem. First, its Σ-Δ ADC uses a 5-bit quantizer resulting in a typical overload level of -0.5 dBFS for a CW tone and a guarantee of no less than -2 dBFS. Second, the AD6676 includes AGC functionality such as a peak power detector with programmable thresholds along with fast IF gain control (via the on-chip attenuator) that can react quickly to a fast ramping blocker. Third, in the event that the AGC is unable to react fast enough, the AD6676 includes the means to detect an overload event that results in instability and recover within a few IQ output samples.
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