Analog.com Analog Dialogue Wiki 简体中文
EngineerZone
EngineerZone
  • Log In
  • Site
  • Search
  • User
  • Support

    Popular Forums

    • RF and Microwave
    • Power Management
    • Video
    • FPGA Reference Designs
    • Precision ADCs
    • Linux Software Drivers
    • SigmaDSP Processors & SigmaStudio Dev. Tool

    Product Forums

    • A2B
    • Amplifiers
    • Analog Microcontrollers
    • Clock and Timing
    • Data Converters
    • Direct Digital Synthesis (DDS)
    • Energy Monitoring and Metering
    • Interface and Isolation
    • MEMS Inertial Sensors
    • Processors and DSP
    • Switches/Multiplexers
    • Temperature Sensors
    • Voltage References
    View All

    Application Forums

    • Audio
    • Automated Test Equipment (ATE)
    • Condition-Based Monitoring
    • Depth, Perception & Ranging Technologies
    • Embedded Vision Sensing Library
    • Motor Control Hardware Platforms
    • Optical Sensing
    • Precision Technology Signal Chains Library
    • Video
    • Wireless Sensor Networks Reference Library

    Design Center Forums

    • ACE Evaluation Software
    • ADEF System Platforms
    • Design Tools and Calculators
    • FPGA Reference Designs
    • Linux Software Drivers
    • Microcontroller no-OS Drivers
    • Reference Designs
    • Signal Chain Power (SCP)
    • Software Interface Tools
    • System Demonstration Platform (SDP) Support
  • Learn

    Highlighted Webinar

    Multidimensional Simulations of Beamformers and other RF Integrated Circuits in Keysight SystemVue

    Recent Discussions

    • Issue running built programs on Pluto
    • Activity: Simple Op Amps, For ADALM1000 Fig. 1.3 Buffering example
    • ADALM-PLUTO [NETWORK] vs [USB_ETHERNET]
    • Using buffer size different from 2**n
    • ADALM1000 Pixelpulse feature Source Voltage / Measure Current explanation

    Places

    • ADI Education Home
    • ADI Education China
    • ADI Education India
    • ADI Education Philippines
    • StudentZone (Analog Dialogue)
    • Virtual Classroom

    Latest Webinars

    • Multidimensional Simulations of Beamformers and other RF Integrated Circuits in Keysight SystemVue
    • Improve Smart Building Energy Efficiency with Industrial Ethernet Controlled Air Conditioning (HVAC) Systems
    • Sustainable Motion Control Solutions for High Performance Servo Drives
    • Audio Design Solutions for Augmented and Virtual Reality (AR/VR) Glasses
    • Robust Industrial Motor Encoder Signal Chain Solutions
    View All Webinars
  • Community Hub

    Challenge Yourself!

      KCC's quizzes AQQ235 about a bipolar common emitter amplifier - a kind proposal from our colleague Martin Walker
    View All

    Places

    • Community Help
    • Logic Lounge

    Resources

    • EZ Code of Conduct
    • Getting Started Guide
    • ADI: Words Matter
    • Community Help Videos
    View All
  • Blogs

    Highlighted Blogs

    Crawl, Walk, And Run - The Journey To Create The Phaser

     

    Hardware Holds The Key To Making Industrial Systems IEC 62443 Compliant

    Latest Blogs

    • Behind the Scenes of DIYRadio Blogs: An Introduction
    • Empowering Surveillance Cameras To Capture A Scene Without Being Heard
    • Mastering The Metrics Makes Specifying Encoders Simpler
    • Understanding Secret Key Cryptography Without Formulas
    • 3 Reasons Why IO-Link is Changing Smart Factory Decision Making
    Read All Blogs

    ADI Blogs

    • EZ Spotlight
    • The Engineering Mind
  • Partners

    Electronic Design Services - PartnerZone

    • Boston Engineering
    • Calian, Advanced Technologies
    • Colorado Engineering Inc. (DBA CAES AT&E)
    • Clockworks Signal Processing
    • Epiq Solutions
    • Fidus
    • PalmSens
    • Richardson RFPD
    • Tri-Star Design, Inc.
    • VadaTech
    • Vanteon
    • X-Microwave
    View All
High-Speed ADCs
  • Data Converters
High-Speed ADCs
Documents I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?
  • Forums
  • File Uploads
  • FAQs/Docs
  • Members
  • Tags
  • More
  • Cancel
  • HIGH-SPEED ADC SUPPORT COMMUNITY
  • TAGS LIST: High-Speed ADCs
  • +Absolute Group Delay: FAQ
  • +AD6620: FAQ
  • +AD6624A: FAQ
  • +AD6633: FAQ
  • +AD6635: FAQ
  • +AD6636: FAQ
  • +AD6640: FAQ
  • +AD6640AST: FAQ
  • +AD6643: FAQ
  • +AD6644: FAQ
  • +AD6645: FAQ
  • +AD664: FAQ
  • +AD6650: FAQ
  • +AD6654: FAQ
  • +AD6655: FAQ
  • +AD6657: FAQ
  • -AD6676: FAQ
    • I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?
    • Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
    • What determines the AD6676’s full-scale input setting?
    • What is the STF response of a Σ-Δ ADC and why does it matter?
    • AD6676 FAQ: Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?
    • AD6676 FAQ: What development tools are available?
    • AD6676 FAQ: What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
    • AD6676 FAQ: Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?
    • AD6676 FAQ: Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
    • AD6676 FAQ: Why isn't the noise floor of the AD6676 flat?
    • AD6676 FAQ:I heard that Σ-Δ ADC’s can be driven into overload resulting in unstable behavior.  Is this true and should I be concerned?
  • +AD9027: FAQ
  • +AD9042: FAQ
  • +AD9050: FAQ
  • +AD9054A: FAQ
  • +AD9057: FAQ
  • +AD9066: FAQ
  • +AD9200: FAQ
  • +AD9201: FAQ
  • +AD9211: FAQ
  • +AD9212: FAQ
  • +AD9215: FAQ
  • +AD9218: FAQ
  • +AD9220: FAQ
  • +AD9222: FAQ
  • +AD9224: FAQ
  • +AD9225: FAQ
  • +AD9228: FAQ
  • +AD9229: FAQ
  • +AD9230: FAQ
  • +AD9231: FAQ
  • +AD9233: FAQ
  • +AD9236: FAQ
  • +AD9238: FAQ
  • +AD9239: FAQ
  • +AD9240: FAQ
  • +AD9243: FAQ
  • +AD9244: FAQ
  • +AD9245: FAQ
  • +AD9246: FAQ
  • +AD9248: FAQ
  • +AD9249: FAQ
  • +AD9250: FAQ
  • +AD9253: FAQ
  • +AD9254: FAQ
  • +AD9255: FAQ
  • +AD9257: FAQ
  • +AD9261: FAQ
  • +AD9262: FAQ
  • +AD9265: FAQ
  • +AD9268: FAQ
  • +AD9266: FAQ
  • +AD9269: FAQ
  • +AD9271: FAQ
  • +AD9272: FAQ
  • +AD9277: FAQ
  • +AD9279: FAQ
  • +AD9280: FAQ
  • +AD9283: FAQ
  • +AD9284: FAQ
  • +AD9286: FAQ
  • +AD9288: FAQ
  • +AD922X: FAQ
  • +AD9410: FAQ
  • +AD9430: FAQ
  • +AD9432: FAQ
  • +AD9433: FAQ
  • +AD9434: FAQ
  • +AD9444: FAQ
  • +AD9446: FAQ
  • +AD9460: FAQ
  • +AD9461: FAQ
  • +AD9467: FAQ
  • +AD9481: FAQ
  • +AD9484: FAQ
  • +AD9520: FAQ
  • +AD9560: FAQ
  • +AD9600: FAQ
  • +AD9613: FAQ
  • +AD9625: FAQ
  • +AD9626: FAQ
  • +AD9627: FAQ
  • +AD9631: FAQ
  • +AD9640: FAQ
  • +AD9643: FAQ
  • +AD9644: FAQ
  • +AD9645: FAQ
  • +AD9649: FAQ
  • +AD9652: FAQ
  • +AD9680: FAQ
  • +AD9683: FAQ
  • +AD9684: FAQ
  • +AD9695: FAQ
  • +AD9814: FAQ
  • +AD9822: FAQ
  • +AD9826: FAQ
  • +AD9864: FAQ
  • +AD9874: FAQ
  • +AD96685: FAQ
  • +High Speed ADC: FAQ
  • +High Speed Capture Data: FAQ
  • +HSC-ADC-EVALCZ: FAQ
  • +JESD204B: FAQ

I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?

Yes, it is possible to reduce the full-scale input requirements by up to 12 dB by reducing the full-scale  current of the 1st feedback DAC (IDAC1FS) from 4 to 1 mA  (refer to Q5).   Reducing the IDAC1FS setting typically results in some dynamic range reduction (due to increased thermal noise contribution and degraded IMD performance) however the amount of degradation is application dependent thus may be worth investigating.  For example, the noise spectral density degrades at a slower rate than the max full-scale input power requirement thus resulting in an actual improvement in the AD6676’s noise figure (NF) at the expense of dynamic range.  Reducing the maximum full-scale input requirement into the AD6676 also allows the preceding RF/IF stage to operate with less gain, possibly reducing the linearity/power of the last state (due to P1dB reduction).  Conversely, operating with a greater margin between the prior stages P1dB and the AD6676’s full-scale input power level allows for greater AGC operating range when using the AD6676’s on-chip attenuator.  In summary, one should consider evaluating the AD6676 at a lower IDAC1FS setting if realizing these potential system level benefits are of interest.

  • Share
  • History
  • More
  • Cancel
Related
Recommended
Social
Quick Links
  • About ADI
  • ADI Signals+
  • Analog Dialogue
  • Careers
  • Contact us
  • Investor Relations
  • News Room
  • Quality & Reliability
  • Sales & Distribution
  • Incubators
Languages
  • English
  • 简体中文
  • 日本語
Newsletter

Interested in the latest news and articles about ADI products, design tools, training and events? Subscribe today!

Sign Up
Analog Logo
©1995 - 2023 Analog Devices, Inc. All Rights Reserved
沪ICP备09046653号-1
  • Sitemap
  • Legal
  • Privacy & Security
  • Privacy Settings
EngineerZone Uses cookies to ensure you get the best experience in our community. For more information on cookies, please read our Privacy & Security Statement.