I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?

Yes, it is possible to reduce the full-scale input requirements by up to 12 dB by reducing the full-scale  current of the 1^st feedback DAC (IDAC1FS) from 4 to 1 mA  (refer to Q5).   Reducing the IDAC1FS setting typically results in some dynamic range reduction (due to increased thermal noise contribution and degraded IMD performance) however the amount of degradation is application dependent thus may be worth investigating.  For example, the noise spectral density degrades at a slower rate than the max full-scale input power requirement thus resulting in an actual improvement in the AD6676’s noise figure (NF) at the expense of dynamic range.  Reducing the maximum full-scale input requirement into the AD6676 also allows the preceding RF/IF stage to operate with less gain, possibly reducing the linearity/power of the last state (due to P1dB reduction).  Conversely, operating with a greater margin between the prior stages P1dB and the AD6676’s full-scale input power level allows for greater AGC operating range when using the AD6676’s on-chip attenuator.  In summary, one should consider evaluating the AD6676 at a lower IDAC1FS setting if realizing these potential system level benefits are of interest.