Data " to output data(CLK Frequency is 100MHz, DCO frequency is 50MHz). And
need to use FPGA to interpolate the I and Q data Rate to 100MHz. So I want to
know how AD6655 to Decimate. That is:
1. For I and Q, which one is output firstly?
2. For decimation, the odd point or even point, which one is decimated?
1) For a given output sample, the I data is output before the Q data. Note
that there is a mistake in the timing diagram in the AD6655 datasheet. Figure
5 shows the I data presented on the rising edge of DCO and the Q data on the
falling edge of DCO. This is inverted – the I data is presented on the falling
edge of DCO and the Q data on the rising edge. For a specific I/Q pair the I
data is presented first. The corrected figure is shown as the attachment.2)
I’m not clear what you mean by the odd point or even point – every other sample
is decimated but I’m not sure how you would designate one sample as odd and the
other as even.