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Documents Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
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  • HIGH-SPEED ADC SUPPORT COMMUNITY
  • TAGS LIST: High-Speed ADCs
  • +Absolute Group Delay: FAQ
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    • I noticed that it is possible to further reduce the full-scale input power requirements to the AD6676.  Is there any trade-offs that I need to be aware of when considering this option?
    • Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
    • What determines the AD6676’s full-scale input setting?
    • What is the STF response of a Σ-Δ ADC and why does it matter?
    • AD6676 Can you explain what the “Profile feature” is and why I it may be advantageous to use in some applications?
    • AD6676 What development tools are available?
    • AD6676 What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?
    • AD6676 Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?
    • AD6676 Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?
    • AD6676 Why isn't the noise floor of the AD6676 flat?
    • AD6676 I heard that Σ-Δ ADC’s can be driven into overload resulting in unstable behavior.  Is this true and should I be concerned?
    • Operating AD6676 at Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.
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Operating AD6676 at  Fadc of 3.26GHz or higher when max allowed specification is 3.2 GHz.

Q 

We like to use your new if-wideband-rx-subsystem AD6676 for our new
tuner generation and I have two question regarding this device:

Our system data rate is 101.875MHz and we like to use the internal
synthesizer and the output decimation filter. If we use the 32
decimation the fadc and fsynthesizer will be 3.26GHz and this is out of
the specification in your datasheet. (fadc and fsynth max. 3.2GHz) We
tested this setting with your eval kit and it seems to work. So how
critical is this 60MHz higher frequency for your device?


We bought the evaluation kit with the HSC-ADC-EVALEZ and we like to save
the captured data for further (our own) analyses in Matlab. Your Matlab
based tool can configure the device and plot the spectrum, IQ-diagram
etc. Is there a possibility to save the captured data in a file? Or can
you provide us the matlab sources from your tool?

 

A 

According to PL, the customer could discover that they can operate the AD6676
and  its CLK SYN up to 4 GHz on the EVB so there is a lot of margin to
accommodate customer's desire to operate at 3.26 GHz.  This is because we
originally designed the ADC core (and CLK SYN) to operate up to 4 GHz clock
rate.However, a max ADC core clock rate has been specified with an upper limit
of 3.2 GHz to ensure that characterization specifications are met over all PVT
(Process, Supply voltage, Temp variations ). This is not guaranteed at ~4GHz.  
According to the PL, they do not see an issue operating it at 3.26 GHz but ADI
cannot guarantee because it is out of specification.

If you are using MATLAB based AD6676 ADC  Analyzer tool,  the 'Save Data'
option under 'Data Display Windows'  in Direct
output mode data window stores the data by default in
'\Results\FFTdata\DataStamp' folder (Section : Data Display Windows (Figure 22)
in Link1).

If you are using VisualAnalog, (AN-905),  AD6676 Samples Canvas -> Graph ->Save
As ->allows you to choose from the currently plotted analysis data and save to
a comma-separated values (.csv) file which can be exported in external
platforms such as MATLAB for further analysis. For capturing data related to
FFT analysis you can choose the respective FFT canvas to store the analysis
data in a similar manner.

References:
VisualAnalogTm Converter Evaluation Tool User Manual Application Note AN-905
http://www.analog.com/media/en/technical-documentation/application-notes/AN-905.pdf 

Tags: ad6676 visualanalog
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