run the *two* AD9216 channels with 50% duty cycle clocks 180 degrees
apart, for interleaving purposes.
The relevant part of the datasheet is page 22 as follows:
The AD9216 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels asyn-
chronously may degrade performance significantly. In some
applications, it is desirable to skew the clock timing of adjacent
channels. The AD9216’s separate clock inputs allow for clock
timing skew (typically ±1 ns) between the channels without
significant performance degradation.
This customer seems to have a good grasp on some important issues, but I would
not make this recommendation to them. I’m not sure that the duty cycle
stabilizer would have any problems, but there are other more fundamental
problems. While he correctly points out that it is silly for us to have 2
clock inputs if they can’t be used for different clock frequencies or phases,
in reality the 2 ADCs need to share the same clock. The crosstalk between the
2 ADCs if they do not share the same clock frequency and phase causes serious
performance problems. If they are comfortable designing an interleaved ADC out
of 2 converters, I would instead recommend that they use single ADCs, like the
AD9214(buffered analog input like the AD9218) or AD9215 (no analog input
buffer). Perhaps a better choice would be for him to consider a part like the
AD9211 200Msps ADC, which would give him the sample rate with no interleaving.