In the datasheet there is no specification of the maximum capacitive load of
the digital outputs of the ADC(I quote in datasheets pg 21 : "...large
capacitive loads...",please define large). We use a 3.3V digital power. Sample
rate @ 125Mhz. The capacitive load for the ADC is 10pF. Is this feasable for
the ADC? Is there a way of simulating with spice?
The AD9246 will drive the 10pF capacitive load. However, for optimal SNR
performance from the AD9246 we do recommend a 5pF output load - with larger
output loads there will be some SNR performance impact due to the output
switching currents (I would estimate about a 1dB SNR impact with 10pF
loading). To achieve the best performance if your output loading is 10pF, we
would recommend using a low input capacitance buffer as keeping the capacitive
loading to a minimum is strongly advised.
We also recommend using slew rate limiting resistors as close to the part as
possible as this will also help limit the switching current as well.