SNR versus input frequency when the clock contains specific levels of jitter.
The theoretical equation for how SNR relates to jitter and input frequency is
contained just above Figure 51. However the graph does not reflect the equation
For instance at 2000MHz 0.2ps of jitter should lead to an SNR of 71dB or so yet
the graph shows around 67dBc.
In my application I am sampling an IF of approximately 150MHz att 120MSPS and
need to achieve an SNR of approx 70dBFS previously I had calculated that I migh
be able to allow close to 0.4ps of jitter on the clock (which would mean the
noise floor on my clock signal would need to be close to -160dBc) however
according to graph 51 this would leave me well short of my requirement. Please
clarify. Is the AD9246-125MSPS likely to be any more sensitive to jitter than
TI's ADS5500 or ADS5545 ? I would also be interested to know the spectral
purity of the clock (in dBc) required to get the datasheet advertised
I also have a question related to the voltage reference options. With internal
reference used either 2Vpk-pk or 1Vpk-pk rnage can be selected depending on
whether sense is grounded or connected to Vref. However I note from table 15
that Vref seems to be adjustable over the SPI. Does this mean that the ADC
rnage can be adjusted over the SPI ? What should sense be connected to in this
case ? Can this feature be used to send a software command to "gain range" the
In Figure 51 the numbers shown on each curve represent the jitter present in
the input clock signal, where the tj in the equation represents the rms sum of
the jitter from all jitter sources. So if you just put the clock jitter into
the equation you will get a better number than shown in the graph. So the
curves on the graph represent the expected performance from the part with a
clock input with the specified jitter. For more detailed information kindly
find Application Note 756 .
In your case if you have an IF at 150MHz and would like to achieve 70dB SNR you
will need a clock source with about 100fs of jitter. The SNR is a result of
the input clock jitter, Ain jitter and the inherent jitter in the converter.
The converter jitter is specified as aperture uncertainty (jitter) and for the
AD9246 this is specd at 100fs. In comparing converter's jitter performance you
can compare these two numbers and also compare the SNR roll off versus analog
input frequency (assuming a fixed sample clock) - a converter with lower jitter
will roll off more slowly than a converter with poor jitter performance.
We typically specify the ADC performance using a Wenzel crystal oscillator.
In regard to the voltage reference when the SENSE pin is connected to AGND
resulting in a default 1.0V Vref and a 2.0V p-p input span the SPI register can
be used to change the input range of the ADC between 2.0V and 1.25V as stated
in the data sheet. As the input span is decreased there is some loss in SNR
performance similar to the difference shown in datasheet Figures 21 and 22 when
moving from 2V p-p input to 1Vp-p.